Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/ EE5342 – Semiconductor Device Modeling and Characterization Lecture 24 - Spring 2004 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/ L24 April 19

Ideal 2-terminal MOS capacitor/diode conducting gate, area = LW Vgate -xox SiO2 y L silicon substrate tsub Vsub x L24 April 19

Band models (approx. scale) metal silicon dioxide p-type s/c Eo qcox ~ 0.95 eV Eo Eo qcSi= 4.05eV qfm= 4.1 eV for Al Ec qfs,p Eg,ox ~ 8 eV EFm Ec EFp EFi Ev Ev L24 April 19

Flat band condition (approx. scale) SiO2 p-Si q(fm-cox)= 3.15 eV q(cox-cSi)=3.1eV Ec,Ox qffp= 3.95eV EFm Ec Eg,ox~8eV EFi EFp Ev Ev L24 April 19

Equivalent circuit for Flat-Band Surface effect analogous to the extr Debye length = LD,extr = [eVt/(qNa)]1/2 Debye cap, C’D,extr = eSi/LD,extr Oxide cap, C’Ox = eOx/xOx Net C is the series comb C’Ox C’D,extr L24 April 19

Accumulation for Vgate< VFB -xox SiO2 EOx,x<0 holes p-type Si tsub Vsub = 0 x L24 April 19

Accumulation p-Si, Vgs < VFB Fig 10.4a* L24 April 19

Equivalent circuit for accumulation Accum depth analogous to the accum Debye length = LD,acc = [eVt/(qps)]1/2 Accum cap, C’acc = eSi/LD,acc Oxide cap, C’Ox = eOx/xOx Net C is the series comb C’Ox C’acc L24 April 19

Depletion for p-Si, Vgate> VFB -xox SiO2 EOx,x> 0 Depl Reg Acceptors p-type Si tsub Vsub = 0 x L24 April 19

Depletion for p-Si, Vgate> VFB Fig 10.4b* L24 April 19

Equivalent circuit for depletion Depl depth given by the usual formula = xdepl = [2eSi(Vbb)/(qNa)]1/2 Depl cap, C’depl = eSi/xdepl Oxide cap, C’Ox = eOx/xOx Net C is the series comb C’Ox C’depl L24 April 19

Inversion for p-Si Vgate>VTh>VFB Vgate> VFB EOx,x> 0 e- e- e- e- e- Depl Reg Acceptors Vsub = 0 L24 April 19

Inversion for p-Si Vgate>VTh>VFB Fig 10.5* L24 April 19

Approximation concept “Onset of Strong Inv” OSI = Onset of Strong Inversion occurs when ns = Na = ppo and VG = VTh Assume ns = 0 for VG < VTh Assume xdepl = xd,max for VG = VTh and it doesn’t increase for VG > VTh Cd,min = eSi/xd,max for VG > VTh Assume ns > 0 for VG > VTh L24 April 19

MOS Bands at OSI p-substr = n-channel Fig 10.9* L24 April 19

Equivalent circuit above OSI Depl depth given by the maximum depl = xd,max = [2eSi|2fp|/(qNa)]1/2 Depl cap, C’d,min = eSi/xd,max Oxide cap, C’Ox = eOx/xOx Net C is the series comb C’Ox C’d,min L24 April 19

MOS surface states** p- substr = n-channel L24 April 19

n-substr accumulation (p-channel) Fig 10.7a* L24 April 19

n-substrate depletion (p-channel) Fig 10.7b* L24 April 19

n-substrate inversion (p-channel) Fig 10.7* L24 April 19

Values for gate work function, fm L24 April 19

Values for fms with metal gate L24 April 19

Values for fms with silicon gate L24 April 19

Typical fms values Fig 10.15* fms (V) NB (cm-3) L24 April 19

Flat band with oxide charge (approx. scale) SiO2 p-Si +<--Vox-->- q(Vox) Ec,Ox q(ffp-cox) q(fm-cox) Ex Eg,ox~8eV EFm Ec EFi EFp q(VFB) Ev VFB= VG-VB, when Si bands are flat Ev L24 April 19

Flat-band parameters for n-channel (p-subst) L24 April 19

Flat-band parameters for p-channel (n-subst) L24 April 19

Inversion for p-Si Vgate>VTh>VFB Vgate> VFB EOx,x> 0 e- e- e- e- e- Depl Reg Acceptors Vsub = 0 L24 April 19

Approximation concept “Onset of Strong Inv” OSI = Onset of Strong Inversion occurs when ns = Na = ppo and VG = VTh Assume ns = 0 for VG < VTh Assume xdepl = xd,max for VG = VTh and it doesn’t increase for VG > VTh Cd,min = eSi/xd,max for VG > VTh Assume ns > 0 for VG > VTh L24 April 19

MOS Bands at OSI p-substr = n-channel Fig 10.9* 2q|fp| qfp xd,max L24 April 19

Computing the D.R. W and Q at O.S.I. Ex Emax x L24 April 19

Calculation of the threshold cond, VT L24 April 19

Equations for VT calculation L24 April 19

Fully biased n-MOS capacitor VG Channel if VG > VT VS VD EOx,x> 0 n+ e- e- e- e- e- e- n+ p-substrate Vsub=VB Depl Reg Acceptors y L24 April 19 L

MOS energy bands at Si surface for n-channel Fig 8.10** L24 April 19

Computing the D.R. W and Q at O.S.I. Ex Emax x L24 April 19

Q’d,max and xd,max for biased MOS capacitor Fig 8.11** xd,max (mm) L24 April 19

Fully biased n- channel VT calc L24 April 19

n-channel VT for VC = VB = 0 Fig 10.20* L24 April 19

References * Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997. **Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986 L24 April 19