332:479 Concepts in VLSI Design Lecture 24 Power Estimation

Slides:

Advertisements

Similar presentations

Topics Electrical properties of static combinational gates:

Advertisements

COMP541 Transistors and all that… a brief overview

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN1600) Lecture 21: Dynamic Combinational Circuit Design Prof. Sherief Reda Division of.

Introduction to CMOS VLSI Design Lecture 18: Design for Low Power David Harris Harvey Mudd College Spring 2004.

S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 14: Power Dissipation Prof. Sherief Reda Division of Engineering, Brown.

Week 7a, Slide 1EECS42, Spring 2005Prof. White Week 7a Announcements You should now purchase the reader EECS 42: Introduction to Electronics for Computer.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 13: Power Dissipation Prof. Sherief Reda Division of Engineering, Brown.

Lecture 13, Slide 1EECS40, Fall 2004Prof. White Lecture #13 Announcements You should now purchase the reader EECS 40: Introduction to Microelectronics,

Lecture 5 – Power Prof. Luke Theogarajan

Lecture 7: Power.

Lecture 7: Power.

Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE VLSI Circuit Design Lecture 8 - Comb. Logic.

Lecture 21, Slide 1EECS40, Fall 2004Prof. White Lecture #21 OUTLINE –Sequential logic circuits –Fan-out –Propagation delay –CMOS power consumption Reading:

The CMOS Inverter Slides adapted from:

EE466: VLSI Design Power Dissipation. Outline Motivation to estimate power dissipation Sources of power dissipation Dynamic power dissipation Static power.

Dec 2010Performance of CMOS Circuits 1 Instructed by Shmuel Wimer Eng. School, Bar-Ilan University Credits: David Harris Harvey Mudd College (Some material.

Washington State University

1 Power Dissipation in CMOS Two Components contribute to the power dissipation: »Static Power Dissipation –Leakage current –Sub-threshold current »Dynamic.

Lecture 10: Circuit Families. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 10: Circuit Families2 Outline  Pseudo-nMOS Logic  Dynamic Logic  Pass Transistor.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 17: October 19, 2011 Energy and Power.

Introduction to CMOS VLSI Design Lecture 9: Circuit Families

Solid-State Devices & Circuits

Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 6.1 EE4800 CMOS Digital IC Design & Analysis Lecture 6 Power Zhuo Feng.

LOW POWER DESIGN METHODS

Damu, 2008EGE535 Fall 08, Lecture 51 EGE535 Low Power VLSI Design Lecture #5 & 6 CMOS Inverter.

COE 360 Principles of VLSI Design Delay. 2 Definitions.

CMOS OUTLINE » Fan-out » Propagation delay » CMOS power consumption.

Lecture 10: Circuit Families

COMP541 Transistors and all that… a brief overview

Smruti R. Sarangi IIT Delhi

Digital Integrated Circuits for Communication

THE CMOS INVERTER.

COMP541 Transistors and all that… a brief overview

Lecture 19: SRAM.

IV UNIT : GATE LEVEL DESIGN

Pass-Transistor Logic

The Inverter EE4271 VLSI Design Professor Shiyan Hu Office: EERC 518

EE40 Lecture 15 Josh Hug 7/30/2010.

LOW POWER DESIGN METHODS V.ANANDI ASST.PROF,E&C MSRIT,BANGALORE.

Lecture 21 OUTLINE The MOSFET (cont’d) P-channel MOSFET

Estimate power saving by clock slowdown for s5378 in 180nm and 32nm CMOS Chao Han ELEC 6270.

October 10, 2017 Kjell Jeppson, Lena Peterson Chapter 5 Power in W & H

Reading: Hambley Ch. 7; Rabaey et al. Sec. 5.2

ELEC 5270/6270 Spring 2013 Low-Power Design of Electronic Circuits Pseudo-nMOS, Dynamic CMOS and Domino CMOS Logic Vishwani D. Agrawal James J. Danaher.

Lecture 10: Circuit Families

COMBINATIONAL LOGIC.

Day 17: October 18, 2010 (Energy) Ratioed Logic

OUTLINE » Fan-out » Propagation delay » CMOS power consumption

Design Technologies Custom Std Cell Performance Gate Array FPGA Cost.

Day 17: October 15, 2012 Energy and Power Basics

Vishwani D. Agrawal James J. Danaher Professor

Introduction to CMOS VLSI Design Lecture 5: DC & Transient Response

CSV881: Low-Power Design Power Dissipation in CMOS Circuits

Introduction to CMOS VLSI Design Lecture 5: Logical Effort

Circuit Characterization and Performance Estimation

COMBINATIONAL LOGIC DESIGN

332:578 Deep Submicron VLSI Design Lecture 14 Design for Clock Skew

Lecture 21 OUTLINE The MOSFET (cont’d) P-channel MOSFET

Lecture 21 OUTLINE The MOSFET (cont’d) P-channel MOSFET

The Inverter EE4271 VLSI Design Dr. Shiyan Hu Office: EERC 731

Lecture 21 OUTLINE The MOSFET (cont’d) P-channel MOSFET

Lecture 7: Power.

Power and Heat Power Power dissipation in CMOS logic arises from the following sources: Dynamic power due to switching current from charging and discharging.

Lecture 7: Power.

Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response

Lecture 10: Circuit Families

Reading: Hambley Ch. 7; Rabaey et al. Secs. 5.2, 5.5, 6.2.1

COMP541 Transistors and all that… a brief overview

ELEC 5270/6270 Spring 2009 Low-Power Design of Electronic Circuits Pseudo-nMOS, Dynamic CMOS and Domino CMOS Logic Vishwani D. Agrawal James J. Danaher.

Presentation transcript:

332:479 Concepts in VLSI Design Lecture 24 Power Estimation David Harris Harvey Mudd College Spring 2004

Concepts in VLSI Des. Lec. 24 Outline Power and Energy Dynamic Power Static Power Low Power Design Summary Material from: CMOS VLSI Design, by Weste and Harris, Addison-Wesley, 2005 11/23/2018 Concepts in VLSI Des. Lec. 24

Concepts in VLSI Des. Lec. 24 Power and Energy Power is drawn from a voltage source attached to the VDD pin(s) of a chip. Instantaneous Power: Energy: Average Power: 11/23/2018 Concepts in VLSI Des. Lec. 24

Concepts in VLSI Des. Lec. 24 Dynamic Power Dynamic power is required to charge and discharge load capacitances when transistors switch. One cycle involves a rising and falling output. On rising output, charge Q = CVDD is required On falling output, charge is dumped to GND This repeats Tfsw times over an interval of T 11/23/2018 Concepts in VLSI Des. Lec. 24

Concepts in VLSI Des. Lec. 24 Dynamic Power Cont. 11/23/2018 Concepts in VLSI Des. Lec. 24

Concepts in VLSI Des. Lec. 24 Dynamic Power Cont. 11/23/2018 Concepts in VLSI Des. Lec. 24

Concepts in VLSI Des. Lec. 24 Activity Factor Suppose the system clock frequency = f Let fsw = af, where a = activity factor If the signal is a clock, a = 1 If the signal switches once per cycle, a = ½ Dynamic gates: Switch either 0 or 2 times per cycle, a = ½ Static gates: Depends on design, but typically a = 0.1 Dynamic power: 11/23/2018 Concepts in VLSI Des. Lec. 24

Concepts in VLSI Des. Lec. 24 Short Circuit Current When transistors switch, both nMOS and pMOS networks may be momentarily ON at once Leads to a blip of “short circuit” current. < 10% of dynamic power if rise/fall times are comparable for input and output 11/23/2018 Concepts in VLSI Des. Lec. 24

Concepts in VLSI Des. Lec. 24 Example 200 Mtransistor chip 20M logic transistors Average width: 12 l 180M memory transistors Average width: 4 l 1.2 V 100 nm process Cg = 2 fF/mm 11/23/2018 Concepts in VLSI Des. Lec. 24

Concepts in VLSI Des. Lec. 24 Dynamic Example Static CMOS logic gates: activity factor = 0.1 Memory arrays: activity factor = 0.05 (many banks!) Estimate dynamic power consumption per MHz. Neglect wire capacitance and short-circuit current. 11/23/2018 Concepts in VLSI Des. Lec. 24

Concepts in VLSI Des. Lec. 24 Dynamic Example Static CMOS logic gates: activity factor = 0.1 Memory arrays: activity factor = 0.05 (many banks!) Estimate dynamic power consumption per MHz. Neglect wire capacitance. 11/23/2018 Concepts in VLSI Des. Lec. 24

Concepts in VLSI Des. Lec. 24 Static Power Static power is consumed even when chip is quiescent. Ratioed circuits burn power in fight between ON transistors Leakage draws power from nominally OFF devices 11/23/2018 Concepts in VLSI Des. Lec. 24

Concepts in VLSI Des. Lec. 24 Ratio Example The chip contains a 32 word x 48 bit ROM Uses pseudo-nMOS decoder and bitline pullups On average, one wordline and 24 bitlines are high Find static power drawn by the ROM b = 75 mA/V2 Vtp = -0.4V 11/23/2018 Concepts in VLSI Des. Lec. 24

Concepts in VLSI Des. Lec. 24 Ratio Example The chip contains a 32 word x 48 bit ROM Uses pseudo-nMOS decoder and bitline pullups On average, one wordline and 24 bitlines are high Find static power drawn by the ROM b = 75 mA/V2 Vtp = -0.4V Solution: 11/23/2018 Concepts in VLSI Des. Lec. 24

Concepts in VLSI Des. Lec. 24 Leakage Example The process has two threshold voltages and two oxide thicknesses. Subthreshold leakage: 20 nA/mm for low Vt 0.02 nA/mm for high Vt Gate leakage: 3 nA/mm for thin oxide 0.002 nA/mm for thick oxide Memories use low-leakage transistors everywhere Gates use low-leakage transistors on 80% of logic 11/23/2018 Concepts in VLSI Des. Lec. 24

Leakage Example (cont’d.) Estimate static power: 11/23/2018 Concepts in VLSI Des. Lec. 24

Leakage Example (cont’d.) Estimate static power: High leakage: Low leakage: 11/23/2018 Concepts in VLSI Des. Lec. 24

Leakage Example (cont’d.) Estimate static power: High leakage: Low leakage: If no low leakage devices, Pstatic = 749 mW (!) 11/23/2018 Concepts in VLSI Des. Lec. 24

Concepts in VLSI Des. Lec. 24 Summary Power and Energy Dynamic Power Static Power Low Power Design 11/23/2018 Concepts in VLSI Des. Lec. 24