SYSTEM BUS

Bus concept: Flow of information Eg: Instruction Data Control signals I/O commands Memory address Register address I/O device address

Memory address: During an instruction fetch Memory address: During an instruction fetch PC to MAR During operand fetch register to MAR Memory data: During an instruction fetch MDR to IR During operand fetch MDR to register

Signals: Data: (Bi-directional) instruction and data Address: (Uni-directional) memory address / peripheral address Control: memory R/W, I/O R/W, interrupt, reset…. CPU : master (Bus Arbitration)

Bus concept:

Instruction fetch : Instruction on address bus Memory read Waits for memory access Takes the content

Operand fetch : Instruction is from one of the registers Memory read Waits for memory access Loads the content to one of the registers

Signals: Interrupt Interrupt acknowledge Hold request Hold acknowledgement Reset Clock Ready

Bus multiplexing: Number of bits in data bus Number of bits in address bus Number of signals in control bus Power supply and ground input pins To reduce pin count and cost. A separate signal (ALE).

Multi purpose microprocessor in PC: Reduction of hardware circuits Better utilization of the processor Design flexibility Open to modification

Operations: POST Bootstrap program / initial program load (IPL) Processor in the PC is responsible

Initialization of the programmable LSIs: PIC PIT PPI CRT controller (CRTC) FDC HDC DMAC Serial communication controller – UART, USART.. Real time calendar / clock Mode of operation Command to be executed

Interface to operating system and IOCS: Hardware BIOS / IOCS System software Application software

I/O BUS COMMUNICATION INTERFACE

Concepts: Attenuation voltage level drop (distributed resistance) Distortion slow rise and fall time ( distributed inductance and capacitance)

CPU-Memory-I/O Architecture I/O module I/O device “I/O bus” “Bus interface” “CPU bus” or “System bus”

Expansion Buses These are “slots” on the motherboard Examples ISA – Industry Standard Architecture PCI – Personal Component Interconnect EISA – Extended ISA SIMM – Single Inline Memory Module DIMM – Dual Inline Memory Module MCA – Micro-Channel Architecture AGP – Accelerated Graphics Port VESA – Video Electronics Standards Association PCMCIA – Personal Computer Memory Card International Association (not just memory!)

3 ISA slots 5 PCI slots 6 SIMM slots 2 DIMM slots Pentium CPU

Serial Interfaces On PCs, a “serial interface” implies a “COM port”, or “communications port” COM1, COM2, COM3, etc. COM ports conform to the RS-232C interface standard, so… No transmission : mark Transmission : space

RS-232C History Defines the interface between a DTE and a DCE Well-established standard, developed by the EIA (Electronics Industry Association) in 1960s Originally intended as an electrical specification to connect computer terminals to modems Defines the interface between a DTE and a DCE DTE = Data Terminal Equipment (terminal) DCE = Data Communications Equipment (modem) A “modem” is sometimes called a “data set” A “terminal” is anything at the “terminus” of the connection VDT (video display terminal), computer, printer, etc.

RS-232C Specifications Data rate Configuration Maximum specified data rate is 20 Kbits/s with a maximum cable length of 15 meters However… It is common to “push” an RS-232C interface to higher data rates Data rates to 1 Mbit/s can be achieved (with short cables!) Configuration Serial, point-to-point

Serial Data Transmission Two modes Asynchronous The transmitting and receiving devices are not synchronized A clock signal is not transmitted along with the data Synchronous The transmitting and receiving devices are synchronized A clock signal is transmitted along with the data (and is used to synchronized the devices) Most (but not all) RS-232C interfaces are asynchronous!

Asynchronous Data Transmission Data are transmitted on the TD (transmit data) line in packets, typically, of 7 or 8 bits Each packet is “framed” by a “start bit” (0) at the beginning, and a “stop bit” (1) at the end Optionally, a “parity bit” is inserted at the end of the packet (before the stop bit) The parity bit establishes either “even parity” or “odd parity” with the data bits in the packet E.g., even parity: the total number of bits “equal to 1” (including the data bits and the parity bit) is an “even number

Data Transmission Example Plot of the asynchronous RS-232C transmission of the ASCII character ‘a’ with odd parity: Idle state Stop bit Start bit Idle state TD 1 ASCII character ‘a’ 7 bits LSB first Parity bit time

DATA COMMUNICATION TO A REMOTE TERMINAL:

COMPONENTS OF SERIAL COMMUNICATION SYSTEM

NATIONAL SEMICONDUCTOR 8250 UART:

MAJOR FEATURES: Baud rate is programmable Generates standard baud rates up to 9600 bauds Can detect a false start bit Raise interrupts

PLUG AND PLAY SYSTEMS

Aim of PnP devices: To automate the configuration process Remove the error prone task of device configuration

Understanding the concepts of PnP: PnP devices (identify itself and the resource requirement) PnP BIOS (need to initialize the core PnP devices) PNP OS (load the appropriate drivers & check the resource requirement of non-PnP devices)

Functions: Identification of installed devices Determination of device resource requirements Creation of a complete system configuration, eliminating all resource conflicts Loading of device drivers Notification of configuration changes

Device types and identification: ISA bus cards PCI bus cards MCA bus cards (MicroChannel Architecture) VESA Local Bus (VLB) cards IDE devices (for hard drivers and CD-ROM drives) SCSI controllers and devices PC card devices Serial port devices (such as MODEMS) Parallel port devices (such as printers)

Detection: used to search for legacy devices during windows setup and you use “add new hardware wizard” Not each start time of windows DETLOG.TXT – basic troubleshooting of devices

Enumeration: Used to identify PnP devices including busses Each time windows starts and during notification (such as insert or remove the devices)

PC ARCHITECTURE

Definition: Coordination of abstract levels of a processor Design Measurement Evaluation Interconnection of various components

PC Architecture / standards: Many levels of advancement In many sectors ( memory, processor, interfaces, peripherals etc.,) Implementation Logical implementation ( Microarchitecture) Circuit implementation (basic elements) Physical implementation ( Interfacing standards) Design implementation ( simulators, emulators, prototypes)

Terms in computer architecture: Macro architecture Instruction Set Architecture (Interface between hardware and software) UISA (Microcode Instruction Set Architecture) Pin architecture

Goals: Cost Memory capacity Latency Throughput Speed MIPS (performance measure) Power consumption