Faster Logic Manipulation for Large Designs Alan Mishchenko Robert Brayton UC Berkeley

Overview Logic representations Disjoint-support decomposition (DSD) Motivation Typical applications Prevalence in benchmarks DSD package Conclusions

Logic Representations Truth tables Sum of products (SOP, CNF) Factored forms BDDs AIGs and TTs DSDs (since 1854?) (since 1959) (since 1983) (since 1986) (since 2000) (since 2012)

Disjoint-Support Decomposition Representation of a Boolean function as a tree of nodes Nodes are logic functions (AND, XOR, etc) Leaf nodes do not overlap (have disjoint support) DSD is full, if functions are only gates (AND, XOR, MUX) Invertors, if present, are edge attributes Comments: Not every function has a full DSD If a full DSD exists, it is canonical XOR AND a b c d

Pros and Cons of Logic Representations Efficiency for small / large functions Canonicity Speed of computing Robustness Size of represen- tation Reveals Boolean properties** TT +++/-- yes ++ -- - SOP/CNF +/+ no + no/yes +/++++ FF +++ BDD ++/++ AIG ++/+++ ++++ DSD ++++/- ** symmetry, unateness, NPN canonicity, decomposability, etc

Motivation for DSD Use Boolean network in SIS Equivalent AIG in ABC a x y f z Equivalent AIG in ABC a b c d f e x y z AIG is a Boolean network of 2-input AND nodes and invertors (dotted lines)

One AIG Node – Many Cuts Combinational AIG Each AIG cut represents a different logic node AIG manipulation with cuts is equivalent to working on many Boolean networks simultaneously f 4-input logic function a b c d e Different cuts for the same node

Computing Logic Function of a Cut S P E D SOP BDD TT TTs are better than BDDs in terms of memory and runtime However, both TTs and BDDs obscure Boolean properties DSD DSDs take less memory/runtime than BDDs/TTs for practical functions of K inputs (8 < K < 16) DSDs explicitly represent Boolean properties Symmetry, unateness, NPN canonicity, decomposition, etc Very important for practical applications!

Logic Operations on Cut Functions AIG Rewriting Technology mapping with Boolean matching Rewriting node A  a b c A Subgraph 1 Subgraph 2 Rewriting node B a b c  B Subgraph 2 Subgraph 1 6-LUT 6 4 6 16-input structure composed of three 6-LUTs

DSD and 1-Step DSD DSD 1-step DSD Represented as a tree whose leaves have disjoint support DSD is full if functions at nodes are only {AND, XOR, MUX}. Invertors are edge attributes. A node without DSD is prime. 1-step DSD There exists variable x such that both cofactors w.r.t. x are full DSDs () <> [] a b d e f g c F(a,b,c,d,e,f,g) = AND(a, MUX(b,!XOR(c,d,e),!AND(f,g))) ()=and, <>=mux, []=xor, !=not

DSD Computation DSDs and 1-DSDs represent functions of the cuts in the AIG during mapping or rewriting At each node, find all K-cuts Each cut defines a function with at most K inputs Compute cut’s DSD by composing DSDs of the fanin cuts Compute NPN canonical form and find it in (or add it to) the unique table in DSD manager Use computed table to reuse the results of intermediate Boolean operations (such as computing AND of two DSDs) How many cut functions are DSD or 1-DSD?

DSD: Prevalence in Benchmarks Table 1A: Percentages of unique functions, NPN classes, and DSDs for different cut sizes (industrial benchmarks). % of functions and classes % of DSDs relative to NPN classes (#DSDs / total n-input NPNs) * 100 % of DSDs relative to the number of cuts (#DSDs / #cuts) * 100 Cut size Cuts Func NPN Full 1-step Total 6 30.0 M 0.88 0.04 6.15 64.32 70.47 93.16 6.24 99.40 8 33.6 M 2.25 0.24 10.91 58.42 69.33 86.28 11.07 97.35 10 35.0 M 3.09 0.59 17.40 49.96 67.36 80.78 14.22 95.00 12 35.6 M 3.73 0.97 21.03 42.08 63.11 75.06 16.87 91.93 14 35.9 M 4.20 1.26 22.02 36.86 58.88 71.06 17.71 88.77 Table 1B: Percentages of unique functions, NPN classes, and DSDs for different cut sizes (public benchmarks). % of functions and classes % of DSDs relative to NPN classes (#DSDs / total n-input NPNs) * 100 % of DSDs relative to the number of cuts (#DSDs / #cuts) * 100 Cut size Cuts Func NPN Full 1-step Total 6 19.8 M 1.68 0.07 4.74 58.38 63.12 89.72 9.32 99.04 8 21.1 M 4.66 0.56 8.27 47.22 55.49 78.48 16.36 94.84 10 21.3 M 6.71 1.46 11.57 37.79 49.37 69.96 19.60 89.56 12 21.7 M 7.92 2.23 12.55 32.69 45.24 63.51 20.93 84.44 14 22.0 M 8.89 2.92 11.99 28.40 40.39 60.36 19.25 79.61

DSD Package Similar to BDD package Different from BDD package Maintains canonical forms Performs Boolean operations Employs computed table Different from BDD package Uses different data structure Used different normalization rules Limited to small practical functions (6-16 inputs) The computed table is more reusable

Primitives of DSD Manager One constant 0 node One primary input node n Multi-input AND nodes with ordered fanins Multi-input XOR nodes with ordered fanins Three-input MUX nodes Multi-input PRIME nodes (w/o DSD; with 1-step DSD) Multi-input PRIME nodes (w/o DSD; w/o 1-step DSD)

Usefulness of DSDs Constructed on-the-fly during cut enumeration No BDDs No TTs Start from elementary variables Derive resulting DSDs by ANDing fanin DSDs Canonicized Unique table (only stores NPN classes of Boolean functions) Cached Computed table If available, the result is returned (e.g. LUT structures matching) If not available, the result is computed and stored

Rules for Canonizing a DSD Collapsing similar functions AND((a,b), AND(c,AND(d,e))) = AND(a,b,c,d,e) Propagating complements to inputs or output AND(!a, !AND(!b, c))  AND(a, !AND(b, c)) AND(!a, !XOR(b, c))  AND(a, XOR(b, c)) AND(a, MUX(b,!AND(c,d),!AND(e,f)))  AND(a,!MUX(b,AND(c,d),AND(e,f))) Using a single variable AND(MUX(d, e, f), a, XOR(b, c))  AND(n, XOR(n, n), MUX(n, n, n)) F = (ab)c and G = d(ef)  AND(n, XOR(n, n)) - same NPN class (Arbitrary but fixed) ordering rules, applied in the increasing order The node fanins are ordered by their support size If tie, AND precedes XOR precedes MUX precedes PRIME If tie, a non-complemented fanin precedes a complemented fanin If tie, fanins’ fanins are ordered and compared in their selected order If recursive comparison of fanin subtrees fails to produce a unique order, the fanins’ DSDs are isomorphic and their order is immaterial

Example of Canonicizing a DSD F(a,b,c,d,e,f,g) = OR( a, !MUX( b, !XOR(c,!e,d), !AND(f,g) ) ) OR () <> [] a b d e f g c () <> [] !a b d e f g c () !a <> b () f g [] d e c ()=and, <>=mux, []=xor, !=not PN = !abfgced

Examples of Full DSDs 2 inputs 3 inputs 4 inputs 5 inputs 6 inputs (ab) (abc) (abcd) (abcde) (abcdef) [ab] (a!(bc)) (a!(b!(cd))) (a[(bc)(de)]) (ab[(cd)(ef)]) [abc] [abcd] (a!(!(bc)!(de)) (!(abc)!(def)) [a(bc)] (a[b(cd)]) (a<b(cd)e>) [a<b[cd][ef]>] (a[bc]) (a<bcd>) <a(bc)(de)> <a(bc)<def>> <abc> <ab[cd]> <a<bc!(de)>> <(ab!(cd))ef> (ab) denotes AND(a,b) [ab] denotes XOR(a,b) <abc> denotes MUX(a, b, c) = ab + !ac First two columns contain all canonical forms using this basis

Case Study: LUT structure mapping 6 4 6 16-input structure composed of three 6-LUTs Comparing run times with truth tables (TTs) with DSDs Application selected because: LUT structure mapping mitigates structural bias of AIG and improves the quality of regular LUT-mapping useful for new generations of programmable devices mapping requires heavy Boolean manipulation implementation in ABC using TTs is prohibitively slow for large designs Preliminary Results (DSDs vs. TTs) Boolean matching on average 30X faster Total runtime of mapping on average 7X faster

References Canonical form Computation from cofactors R. L. Ashenhurst, “The decomposition of switching functions”. Computation Lab, Harvard University, 1959, Vol. 29, pp. 74-116. Computation from cofactors V. Bertacco and M. Damiani, "Disjunctive decomposition of logic functions," Proc. ICCAD ‘97, pp. 78-82. Computation from cofactors (corrections) Y. Matsunaga, "An exact and efficient algorithm for disjunctive decomposition", Proc. SASIMI '98, pp. 44-50. Alternative computations T. Sasao and M. Matsuura, "DECOMPOS: An integrated system for functional decomposition," Proc. IWLS ’98, pp. 471-477. S.-I. Minato and G. De Micheli, “Finding all simple disjunctive decompositions using irredundant sum-of-products forms”. Proc. ICCAD’98, pp. 111-117. Boolean operations S. Plaza and V. Bertacco, "Boolean operations on decomposed functions", Proc. IWLS ’05. Applications in synthesis and mapping A. Mishchenko, R. K. Brayton, and S. Chatterjee, "Boolean factoring and decomposition of logic networks", Proc. ICCAD'08, pp. 38-44.

Conclusion DSDs are an interesting representation Effective only for small, practical functions! DSDs reveal Boolean properties and facilitate Rewriting Technology mapping Factoring DSDs lead to larger scope (cut depth) than TTs Most operations are local but repeated often Memory usage and runtime are improved due to Canonicity (unique table in the DSD manager) Result caching (computed table in the DSD manager)

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