Memory Devices on DE2-115 Digital Circuit Lab TA: Po-Chen Wu.

Slides:



Advertisements
Similar presentations
Introduction to PIC Microcontrollers
Advertisements

The ESA MUSIC Project Design of DSP HW and Analog TX/RX ends Advanced Mobile Satellite Systems & Technologies presentation days ESA/ESTEC – November.
VHDL 8 Practical example
Chapter 5 Internal Memory
Memory Section 7.2. Types of Memories Definitions – Write: store new information into memory – Read: transfer stored information out of memory Random-Access.
Programmable Logic PAL, PLA.
Microprocessor System Design. Outline Address decoding Chip select Memory configurations.
LOGO.  Concept:  Is read-only memory.  Do not lose data when power is lost.  ROM memory is used to produce chips with integrated.
Altera FLEX 10K technology in Real Time Application.
Chapter 10. Memory, CPLDs, and FPGAs
Programmable logic and FPGA
CS 151 Digital Systems Design Lecture 30 Random Access Memory (RAM)
Aztec PC Scope Preliminary Design Review Fall 2006 Michael MasonJed Brown Andrew YoungsJosh Price.
Chapter 5 Internal Memory
Aztec PC Oscilloscope Michael Mason Jed Brown Josh Price Andrew Youngs.
CSCE 430/830 A Tutorial of Project Tools By Dongyuan Zhan Feb. 4, 2010.
NS Training Hardware. Memory Interface Support for SDRAM, asynchronous SRAM, ROM, asynchronous flash and Micron synchronous flash Support for 8,
MEMORY.
DE2-115 Control Panel - Part II
16x2 LCD Module on DE2-115 數位電路實驗 TA: 吳柏辰 Author: Trumen.
This Thursday, Oct. 25 th 1-1:50pm: Exam in DUANE G140 Covers lectures and labs (except today’s lecture on microcontrollers) You may bring handwritten.
9/20/6Lecture 3 - Instruction Set - Al1 Interfacing Devices to the
DDR MEMORY  NEW TCEHNOLOGY  BANDWIDTH  SREVERS, WORKSTATION  NEXT GENERATION OF SDRAM.
University of Tehran 1 Microprocessor System Design Omid Fatemi Memory Interfacing
CS-280 Dr. Mark L. Hornick 1 Parts of a GP Computer (Microcomputer) Contains separate Microprocessor chip Memory/Memory controller MB control chips Peripheral.
Memory and Programmable Logic
A+ Guide to Managing and Maintaining Your PC Fifth Edition Chapter 6 Managing Memory.
Chapter 5 Internal Memory. Semiconductor Memory Types.
HARDWARE ARCHITECTURE
COMPUTER SCIENCE Data Representation and Machine Concepts Section 1.2 Instructor: Lin Chen August 2013.
Memory Interface A Course in Microprocessor Electrical Engineering Dept. University of Indonesia.
Digital Design: Principles and Practices
Memory Devices on DE2-115 數位電路實驗 TA: 吳柏辰 Author: Trumen.
Memory characteristics Ideal Access time (minimum). Nonvolatile. Stored data can be modified. Minimum space (very dense). Minimum current drain (power.
AT91 Memory Interface. 2 Features –Up to 8 programmable chip select lines –Remap Command allows dynamic exception vectors –Glue-less for both 8-bit and.
9/20/6Lecture 12 - Interfacing Devices1 Interfacing Devices to the
Interfacing External Memory Rajiv Nandivada. High Level Schematic Clock cycle of ns (Depending on its use). 3.3 V CMOS SRAM (128 x 8 bit). Uses.
System Software Design Review.  MCU: NXP LPC2378 ARM7 32-bit  512 KB Flash, 8KB EEPROM and SRAM  Bus Frequency: 20 MHz  Approximate Memory requirements:
Digital Circuits Introduction Memory information storage a collection of cells store binary information RAM – Random-Access Memory read operation.
Multiplexors Decoders  Decoders are used for forming separate signals for different combination of input signals.  The multiplexer circuit is a digital.
Logic and Computer Design Fundamentals, Fifth Edition Mano | Kime | Martin Copyright ©2016, 2008, 2004 by Pearson Education, Inc. All rights reserved.
© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Logic Design Dr. Oliver Faust.
VHDL Models For Memory And Busses 구 본 진.
Submitted To: Submitted By: Seminar On 8086 Microprocessors.
Memory Mapped IO (and the CerfBoard). The problem How many IO pins are available on the 8051? What if you are using interrupts, serial, etc…? We want.
Physical Memory and Physical Addressing ( Chapter 10 ) by Polina Zapreyeva.
8255 Programmable Peripheral Interface
DE2-115 Control Panel - Part I
COMP211 Computer Logic Design
Memory Interfacing.
DE2-115 Control Panel - Part II
CPU1 Block Specifications
9S12C Multiplexed Bus Expansion
Memory Systems 7/21/2018.
16x2 LCD Module on DE2-115 Digital Circuit Lab TA: Po-Chen Wu.
Lecture 11: External SRAM
MEMORY/SRAM SIMULATOR LAB
Semiconductor Contact Probe Aligner
EE345: Introduction to Microcontrollers Memory
AT91 Memory Interface This training module describes the External Bus Interface (EBI), which generatesthe signals that control the access to the external.
Digital Logic & Design Dr. Waseem Ikram Lecture 40.
Introduction to VGA Digital Circuit Lab TA: Po-Chen Wu.
The Nostalgic 4 ECE 477 Group 5 Peter Salama John Mastarone
MICROPROCESSOR MEMORY ORGANIZATION
UNIT-III Pin Diagram Of 8086
NS Training Hardware.
Speaker: Yu-Ju Cho 卓余儒 Advisor: Prof. An-Yeu Wu 吳安宇教授
Arduino Board.
Arduino म्हणजे काय?.
FIGURE 7-1 Block Diagram of Memory
Presentation transcript:

Memory Devices on DE2-115 Digital Circuit Lab TA: Po-Chen Wu

Outline SRAM SDRAM FLASH EEPROM SD Card

SRAM

Features 16M-bit (2MB) static RAMs organized as 1024K words by 16 bits. High-speed access times: speed = 20ns for VDD 1.65V to 2.2V speed = 10ns for VDD 2.4V to 3.6V speed = 8ns for VDD 3.3V + 5% # of addresses Maximum performance frequency: 125MHz

Schematic Diagram

SRAM Pin Assignments Signal Name FPGA Pin No. Description SRAM_ADDR[0]~ PIN_AB7~ SRAM Address[0]~ SRAM_DQ[0]~ PIN_AH3~ SRAM Data[0]~ SRAM_OE PIN_AD5 SRAM Output Enable SRAM_WE PIN_AE8 SRAM Write Enable SRAM_CE PIN_AF8 SRAM Chip Enable SRAM_LB PIN_AD4 SRAM Lower Byte Control SRAM_UB PIN_AC4 SRAM Upper Byte Control

SRAM Block Diagram

SRAM Pin Configuration 48-pin TSOP-1 (12mm x 20mm)

Truth Table

Read Cycle Min. read cycle time tRC = 8ns

Write Cycle Min. write cycle time tWC = 8ns

The End. Any question?

Reference "DE2-115 User Manual" by Terasic. "DE2-115_MB.pdf" by Terasic. "61WV102416ALL(ISSI_1M x 16_SRAM).pdf" by ISSI.