Introduction to Micro Controllers & Embedded System Design Addressing Mode Department of Electrical & Computer Engineering Missouri University of Science & Technology hurson@mst.edu A.R. Hurson

Introduction to Micro Controllers & Embedded System Design Note, this unit will be covered in two lectures. In case you pre-test it, then you have the following options: 1) Take the early test and start module5 2) Study the supplement module (supplement.module4) 3) Act as a helper to help other students in studying module1 Note, options 2 and 3 have extra credits as noted in course outline.

  Introduction to Micro Controllers & Embedded System Design Enforcement of background Glossary of prerequisite topics No Familiar with the topics? Review background for this module Yes Take Test At the end: take exam, record the score, impose remedial action if not successful No Pass? Remedial action  Yes Glossary of topics Current Module No Familiar with the topics? Take the Module Yes Take Test No Pass? Yes Options Lead a group of students in this module (extra credits)? Study next module? Study more advanced related topics (extra credits)? Extra Curricular activities

8051 supports the following addressing modes: Register Implied Direct Indirect Immediate Relative Absolute Long Indexed A.R. Hurson

Register addressing In 8051 programmer has access to eight “working registers” numbered R0 to R7. Three least significant bits of op.code are used to specify a register. The 8051 assembly language indicates register addressing with the symbol Rn (0  n  7). A.R. Hurson

Instruction format Register addressing Op.code Register Example ADD A, R7  1 1 1 0 1 1 1 1 register Op.code Op.code Register Instruction format A.R. Hurson

Register addressing Example: Is MOV R4, R7 a valid instruction? No. Note: We can move data between accumulator and Rn, 0  n  7 but we cannot move data between Rn registers. A.R. Hurson

Register addressing Note: The source and destination registers must match in size. Hence, MOV DPTR, A will give an error. How to move a large value to registers? See the following: MOV DPTR, #25F5H MOV R7, DPL MOV R6, DPH A.R. Hurson

Register addressing Note: MOV A, R7 is the same as MOV A, 7 A.R. Hurson

Register addressing Note: we can move data between accumulator and Rn ( 0  n  7), but we cannot move data between Rn registers directly. As the result, the following instruction is illegal. MOV R5 , R7 A.R. Hurson

Implied Some instructions are referring to specific register such as A (accumulator), DPTR (data pointer), PC (program counter), and B register so address bits are not needed. In another words, op.code indicates the register involved in the operation. Example INC DPTR MUL AB A.R. Hurson

Instruction format Direct addressing Op.code Direct addressing Direct addressing allows access to any on-chip variable or hardware register. An additional byte is appended to the op.code specifying the location to be used. Example MOV P1, A Op.code Direct addressing Instruction format A.R. Hurson

Direct addressing Example MOV R7, 40H ; Content of RAM location 40H is saved in R7 MOV 56H, A ; Content of accumulator is saved in RAM location 56H MOV A, R2 ; Content of R2 is saved in accumulator MOV A, 2 ; Content of R2 is saved in accumulator MOV A, #2 ; Accumulator is initialized by 2 MOV A, 55H ; Content of RAM location 55H is saved in accumulator A.R. Hurson

Indirect addressing In 8051, R0 and R1 may operate as a “pointer” register. In this case, the low order bit of op.code indicates which register. In 8051assembly language, indirect addressing is identified as “@” preceding either R0 or R1. A.R. Hurson

Instruction format Indirect addressing i Op.code Example: Assume R1 contains 40H and internal memory address 40H contains 55H, then the instruction MOV A, @R1 moves 55H into the accumulator i Op.code R0 or R1 Instruction format A.R. Hurson

Indirect addressing The following code clears RAM locations at addresses 60H to 7FH: MOV R0, #60H LOOP: MOV @R0, #0 INC R0 CJNE R0, #80H, Loop  A.R. Hurson

Instruction format Immediate addressing Op.code Immediate data In assembly language of 8051, immediate addressing is identified by “#” symbol. The operand may be a numeric constant, a symbolic variable, or an arithmetic expression using constant, symbols, and operators. Assembler calculates the expression and substitutes the result into the instruction. Op.code Immediate data Instruction format A.R. Hurson

Immediate addressing Example: Is MOV DPTR, #68975 a valid instruction? No! 68975 > 65535 is too large Note: We can move data between accumulator and Rn, 0  n  7 but we cannot move data between Rn registers. A.R. Hurson

Immediate addressing Example: MOV A, #12 Note: There is just one exception when initializing the data pointer, we need a 16-bit constant, therefore MOV DPTR, #8000H is a 3-byte instruction with a 16-bit constant 8000H. A.R. Hurson

Immediate addressing COUNT EQU 30  MOV R4, #COUNT ; R4 = 1EH MOV DPTR, #MYDATA ; DTPR = 200H ORG 200H MYDATA: DB “America” A.R. Hurson

Example: Write a program to copy value 55H into RAM locations 40H to 45H using; Direct addressing mode Register indirect addressing mode With a loop A.R. Hurson

Direct addressing mode MOV A, #55H ; Load accumulator with 55H MOV 40H, A ; Load accumulator to location 40H MOV 41H, A ; Load accumulator to location 41H MOV 42H, A ; Load accumulator to location 42H MOV 43H, A ; Load accumulator to location 43H MOV 44H, A ; Load accumulator to location 44H A.R. Hurson

Register indirect addressing mode MOV A, #55H ; Load accumulator with 55H MOV R0, #40H ; Load the pointer MOV @R0, A ; Load A to location pointed by R0 INC R0 ; Increment pointer A.R. Hurson

MOV A, #55H ; Load accumulator with 55H With a loop MOV A, #55H ; Load accumulator with 55H MOV R0, #40H ; Load the pointer MOV R2, #05 ; Load the loop counter AGAIN: MOV @R0, A ; Load A to location pointed by R0 INC R0 ; Increment pointer DJNZ R2, AGAIN ; Repeat until counter is zero A.R. Hurson

Analyze the following program ORG 0000H MOV DPTR, #200H CLR A MOVC A, @A+DPTR ; Load the pointer MOV R0, A ; Load the loop counter INC DPTR MOVC A, @A+DPTR MOV R1, A MOV R2, A HERE: SJMP HERE ; Infinite loop ORG 200H MYDATA: DB “USA” ; Data is stored at address 200H END ; End of program A.R. Hurson

Analyze the following program ORG 0000H MOV DPTR, #MYDATA MOV R0, #40H BACK: CLR A MOVC A, @A+DPTR MOV @R0, A INC DPTR INC R0 DJNZ R2 , BACK HERE: SJMP HERE ORG 250H MYDATA: DB “AMERICA” ; Data is stored at address 250H END ; End of program A.R. Hurson

Analyze the following program ORG 0000H MOV DPTR, #MYDATA MOV R0, #40H BACK: CLR A MOVC A, @A+DPTR JZ HERE MOV @R0, A INC DPTR INC R0 SJMP BACK HERE: SJMP HERE ORG 250H MYDATA: DB “AMERICA”, 0 ; Data is stored at address 250H END ; End of program A.R. Hurson

Analyze the following program ORG 0000H MOV DPTR, #300H MOV A, #0FFH MOV P1, A BACK: MOV A, P1 MOVC A, @A+DPTR MOV P2, A SJMP BACK ORG 300H XSQRT: DB 0, 1, 4, 9, 16, 25, 36, 49, 64, 81 END A.R. Hurson

Instruction format Relative addressing Op.code Relative offset This addressing mode is used with certain jump instructions. A relative address is an 8-bit signed value which is added to the contents of the program counter to form address of the next instruction to be fetched and executed. Naturally, the range for jump is -128 to +127 locations. Op.code Relative offset Instruction format A.R. Hurson

Relative addressing Example: Assume label THREE represents an instruction at location 1040H and instruction SJMP THREE is in memory location 1000H and 1001H, then the assembler assigns a relative offset of 3EH as byte-two of the instruction since 1002H + 3EH = 1040H A.R. Hurson

 Calculating off set for Relative addressing 010A 0109 0108 0107 5 0106 4 0105 3 0104 2 0103 1 0102 0101 05 0100 80 00FF SJMP 0107H  PC A.R. Hurson

 Calculating off set for Relative addressing 2043 2042 2041 F6 -1 2040 80 -2 -3 -4 -5 -6 -7 -8 -9 -10  PC SJMP 2038H A.R. Hurson

Instruction format Absolute addressing Op.code A7-A0 Absolute addressing is just used with ACALL and AJMP instructions. These 2-byte instructions allow branching within the current 2K page of code memory by providing the 11 least significant bits of destination address in op.code (i.e., A10-A8 and byte 2 of instruction A7-A0). A10-A8 Op.code A7-A0 Instruction format A.R. Hurson

Absolute addressing The upper five bits of the destination address are the current value of the upper five bits of program counter. Therefore, the next instruction after the branch and the destination instruction must be within the same 2K page. A.R. Hurson

Absolute addressing  2K page31 32 2K pages. Within each FFFF F800 2K page31 32 2K pages. Within each the upper 5 address bits are common. 17FF 1000 2K page2 0FFF 0800 2K page1 07FF 0000 2K page0 A.R. Hurson

Instruction format Long addressing A15-A8 A7-A0 Long addressing is used with LCALL and LJMP instructions. These instruction are 3 bytes long. Bytes 2 and 3 form the 16-bit destination address. Op.code A15-A8 A7-A0 Instruction format A.R. Hurson

PC or DPTR + ACC = effective address Index addressing Index addressing uses a base register (either the program counter or the data pointer) and an offset (the accumulator) in forming the effective address for JMP or MOVC instructions. Example: MOVC A, @A+PC PC or DPTR + ACC = effective address Base register Offset A.R. Hurson

Special Function Registers (SFR) Symbol Name Address ACC* Accumulator 0E0H B* B register 0F0H PSW* Program status word 0D0H SP Stack Pointer 81H DPTR DPL DPH Data Pointer (2 bytes) Low byte High byte 82H 83H P0* Port 0 80H P1* Port 1 90H P2* Port 2 0A0H P3* Port 3 oB0H IP* Interrupt priority control 0B8H A.R. Hurson

Special Function Registers (SFR) Symbol Name Address IE Interrupt enable control 0A0H TMOD Timer/counter mode control 89H TCON* Timer/counter control 88H T2CON* Timer/counter 2 control 0C8H T2MOD 0C9H TH0 Timer/counter 0 high byte 8CH TL0 Timer/counter 0 low byte 8AH TH1 Timer/counter 1 high byte 8DH TL1 Timer/counter 1 low byte 8BH A.R. Hurson

Special Function Registers (SFR) Symbol Name Address TH2 Timer/counter 2 high byte 0CDH TL2 Timer/counter 2 low byte 0CCH RCAP2H T/C capture register high byte 0CBH RCAP2L T/C capture register low byte 0CAH SCON* Serial control 98H SBUF Serial data buffer 99H PCON Power control 87H * Bit addressable A.R. Hurson