Introduction to VLSI Programming Lecture 7: Introduction to the DLX (course 2IN30) Prof. dr. ir.Kees van Berkel

Time table 2005 date class | lab subject Aug. 30 2 | 0 hours intro; VLSI Sep. 6 3 | 0 hours handshake circuits Sep. 13 handshake circuits assignment Sep. 20 Tangram Sep. 27 no lecture Oct. 4 Oct. 11 1 | 2 hours demo, fifos, registers | deadline assignment Oct. 18 design cases; Oct. 25 DLX introduction Nov. 1 low-cost DLX Nov. 8 high-speed DLX Nov. 29 deadline final report 11/24/2018 Kees van Berkel

VLSI programming for … Low costs: introduce resource sharing. Low delay (high throughput): introduce parallelism. Low energy (low power): reduce activity; … 11/24/2018 Kees van Berkel

VLSI programming for low costs Keep it simple!! Introduce resource sharing: commands, auxiliary variables, expressions, operators. Enable resource sharing, by: reducing parallelism making similar commands equal 11/24/2018 Kees van Berkel

Procedure definition vs declaration Procedure definition: P = proc (). S provides a textual shorthand (expansion) each call generates copy of resource, i.e. no sharing Procedure declaration: P : proc (). S defines a sharable resource each call generates access to this resource 11/24/2018 Kees van Berkel

Hints and Tips: optimization When asked to optimize for area (low cost) it is allowed to invest time (execution time, extra iterations, …) When asked to optimize for speed, it is allowed to invest area (pipeline stages, parallelism, …) 11/24/2018 Kees van Berkel

Hints and Tips: a known bug Statement of form if –x then S0 else S1 fi During simulation wrong alternative is selected (e.g. S0 when x = true) Work around: remove negation: if x then S1 else S0 fi 11/24/2018 Kees van Berkel

Instruction Set Architecture ISA is interface between hardware and software. Hence, a good ISA: allows easy programming (compilers, OS, ..); allows efficient implementations (hardware); has a long lifetime (survives many HW generations); is general purpose. 11/24/2018 Kees van Berkel

ISA classification Code sequence for C:= A+B 11/24/2018 Kees van Berkel

Reduced Instruction Set Computer 1980: Patterson and Ditzel: “The Case for RISC” fixed 32-bit instruction set, with few formats load-store architecture large register bank (32 registers), all general purpose On processor organization: hard-wired decode logic pipelined execution single clock-cycle execution 11/24/2018 Kees van Berkel

RISC processors Advantages: smaller die size (single chip processor) shorter development time (simplicity) higher performance Disadvantages: poor code density cannot execute X86 code 11/24/2018 Kees van Berkel

A “Typical” RISC 32-bit instructions, 3 fixed formats 32 general purpose registers, 32-bit 3 address arithmetic instructions, reg-reg single address mode for load/store: “address + displacement” simple branch conditions; delayed branch 11/24/2018 Kees van Berkel

DLX (“Deluxe”) (AMD 29K + DECstation 3100 + HP850 + IBM801 + Intel i860 + MIPS M/120A + MIPS M/1000 + Motorola 88K + RISC I + SGI 4D/60 + SPARCstation-1 + Sun 4/110 + Sun-4/260) / 13 = DLX Other RISC examples include: Cray-1,2,3, AMD2900, DEC Alpha, ARM. 11/24/2018 Kees van Berkel

DLX instruction formats 31 26, 25 21, 20 16, 15 11, 10 0 Opcode Reg-reg ALU operations rs1 rd rs2 function R-type Opcode loads, stores, conditional branch, .. rs1 rd Immediate I-type offset Opcode Jump, jump and link, trap, return from exception J-type 11/24/2018 Kees van Berkel

Example instructions 11/24/2018 Kees van Berkel

GCD in GCL x,y:= X,Y ; do xy  if x>y  x:= x-y [] x<y  y:= y-x fi od { R: x=gcd(X,Y) } 11/24/2018 Kees van Berkel

GCD in DLX assembler pre: LW R1,4(R0) R1:=Mem[4+0] loop: SUB R3,R1,R2 R3:=R1-R2 BEQZ R3,”exit” if (R3=0) then PC:=“exit” SLT R4,R1,R2 R4:=(R1<R2) BEQZ R4,”pos2” if (R4=0) then PC:=“pos2” pos1: SUB R2,R2,R1 R2:=R2-R1 J “loop” PC:=“loop” pos2: SUB R1,R1,R2 R1:=R1-R2 exit: SW 20(R0),R1 Mem[20+0]:=R1 HLT 11/24/2018 Kees van Berkel

DLX instruction mixes [from H&P, Figs 2.26, 2.27] 11/24/2018 Kees van Berkel

DLX interface, state Instruction memory Mem (Data memory) address r0 pc r1 r2 DLX CPU Reg instruction data r/w r31 clock interrupt 11/24/2018 Kees van Berkel

DLX: “Moore machine” (ignoring interrupts) Reg[0],pc  := 0,0 ; do Mem[Reg[rs1 +immediate], pc, Reg[rd]  :=  if SW  Reg[rs1+immediate] fi , if J  pc+4+offset [] BEQZ  if Reg[rs]=0  pc+4 +immediate [] Reg[rs]#0  pc+4 fi [] else  pc+4 fi , if LW  Mem[rs1+immediate] [] ADD  ALU(add, Reg[rs1], Reg[rs2]) fi  od 11/24/2018 Kees van Berkel

DLX: 5-step sequential execution 11/24/2018 Kees van Berkel

DLX: 5-step sequential execution IF ID EX MM WB Reg A B Imm ir npc pc aluo cond lmd 0? Instr. mem 4 Mem 11/24/2018 Kees van Berkel

Bibliography Computer Architecture; a Quantitative Approach (3rd Ed.); John L Hennessy & David A Patterson; Morgan Kaufmann Publishers Inc, 1996. ARM System Architecture; Steve Furber; Addison Wesley, 1996. DSP Processor Fundamentals, Architectures and Features; Phil Lapsey et al (Berkeley Design Technology Inc.), IEEE, 1996. www.handshakesolutions.com www.arm.com/news/6936.html www.research.philips.com/ newscenter/archive/2004/handshake.html 11/24/2018 Kees van Berkel

Some references www.handshakesolutions www.arm.com/news/6936.html www.research.philips.com/ newscenter/archive/2004/handshake.html 11/24/2018 Kees van Berkel

Next week: lecture 8 Outline: VLSI programming for high performance. Pipelining the DLX. Lab work: Assignment 4 (improve the performance of the Tangram DLX.) 11/24/2018 Kees van Berkel