Chapter 1 Interconnect Extraction Prof. Lei He Electrical Engineering Department University of California, Los Angeles URL: eda.ee.ucla.edu Email: lhe@ee.ucla.edu

Outline Capacitance Extraction Introduction Table based method Formula based method Inductance Extraction RLC circuit model generation Full model and normalized model Inductance truncation via L-1 model Finite element method (FEM) based Extraction Overview of FEM FEM based Extraction Flow Homework

Lm(wire21, wire12) / sqrt(L21 * L12) Full RLC Circuit Model Ls(wire12) $$ Self inductance $$ L11 N11 N12 val L12 N13 N14 val L21 N21 N22 val L22 N23 N24 val $$ mutual inductance $$ K1 L11 L21 val K2 L12 L22 val K3 L11 L12 val K4 L21 L22 val K5 L11 L22 val K6 L21 L12 val N11 N13 N12 N14 N21 N23 N22 N24 For n wire segments per net RC elements: n self inductance: n mutual inductance: n*(n-1) Lm(wire21, wire12) / sqrt(L21 * L12)

Normalized RLC Circuit Model Ls(net1) $$ Self inductance $$ L11 N11 N12 val L12 N13 N14 val L21 N21 N22 val L22 N23 N24 val $$ mutual inductance $$ K1 L11 L21 val K2 L12 L22 val N11 N13 N12 N14 N21 N23 N22 N24 For n segments per wire RC elements: n Self inductance: n Mutual inductance: n Lm(net1, net2) / sqrt(net1 * net2)

Full Versus Normalized Two waveforms are almost identical Running time: Full 99.0 seconds Normalized 9.1 seconds

Application of RLC model Shielding Insertion: To decide a uniform shielding structure for a given wide bus Ns: number of signal traces between two shielding traces Ws: width of shielding traces Ws Ws Ws ... ... 1 2 3 Ns 1 2 3 Ns

Trade-off between Area and Noise Total 18 signal traces 2000um long, 0.8um wide separated by 0.8um Drivers -- 130x; Receivers -- 40x Power supply: 1.3V Ns Ws Noise(v) Routing Area (um) Wire Area (um) 18 -- 0.71 61.1(0.0%) 46.4(0.0%) 6 0.8 0.38 64.8 48.0 6 1.6 0.27 66.4 49.6 6 2.4 0.22 68.0 51.2 3 0.8 0.17 69.6(13%) 50.4(8.8%)

References Original paper: M. Xu and L. He, "An efficient model for frequency-based on-chip inductance," IEEE/ACM International Great Lakes Symposium on VLSI, West Lafayette, Indiana, pp. 115-120, March 2001. More detailed justification: Tao Lin, Michael W. Beattie, Lawrence T. Pileggi, "On the Efficacy of Simplified 2D On-Chip Inductance Models," pp.757, 39th Design Automation Conference (DAC'02), 2002

Outline Capacitance Extraction Introduction Table based method Formula based method Inductance Extraction RLC circuit model generation Full model and normalized model Inductance truncation via L-1 model Finite element method (FEM) based Extraction Overview of FEM Frequency-independent extraction Frequency-dependent extraction Homework

Inductance Screening Accurate modeling the inductance is expensive Only include inductance effect when necessary How to identify?

Off-chip Inductance screening The error in prediction between RC and RLC representation will exceed 15% for a transmission line if CL is the loading at the far end of the transmission line l is the length of the line with the characteristic impedance Z0

Conditions to Include Inductance Based on the transmission line analysis, the condition for an interconnect of length l to consider inductance is R, C, L are the per-unit-length resistance, capacitance and inductance values, respectively tr is the rise time of the signal at the input of the circuit driving the interconnect

On-chip Inductance Screening Difference between on-chip inductance and off-chip inductance We need to consider the internal inductance for on-chip wires Due to the lack of ground planes or meshes on-chip, the mutual couplings between wires cover very long ranges and decrease very slowly with the increase of spacing. The inductance of on-chip wires is not scalable with length.

On-Chip Self Inductance Screening Rules The delay and cross-talk errors without considering inductance might exceed 25% if where fs = 0.34/tr is called the significant frequency

On-Chip Mutual Inductance Screening Rules Empirical rules (2x rule) Most of the high-frequency components of an inductive signal wire will return via its two quiet neighboring wires (which may be signal or ground) of at least equal width running in parallel The potential victim wires of an inductive aggressor (or a group of simultaneously switching aggressors) are those nearest neighboring wires with their total width equal to or less than twice the width of the aggressor (or the total width of the aggressors) Wires of reversed switching are more effective for current return compared to quiet wires

Matrix-based Inductance Sparsification/Screening Capacitance Matrix Sparsification Capacitance is a local effect Directly truncate off-diagonal small elements produces a sparse matrix. Guaranteed stability (no negative eigenvalue)

Inductance Matrix Sparsification L Matrix Sparsification Inductance is not a local effect L matrix is not diagonal dominant Directly truncating off-diagonal elements cannot guarantee stability

Inductance Matrix Sparsification Direct Truncation of

References Original paper: Devgan, A., Ji, H., and Dai, W. “How to efficiently capture on-chip inductance effects: introducing a new circuit element K”. International Conference on Computer Aided Design (ICCAD), 2000. Double Inversion: Kaushik Roy, Cheng-Kok Koh, and Guoan Zhong, “On-chip interconnect modeling by wire duplication “, ICCAD, 2002 Simulator for k-element: Hao Ji, Anirudh Devgan and Wayne Dai, “KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect ”. ASP-DAC '01.

Reading Assignment [1] Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Lei He, “Clocktree RLC Extraction with Efficient Inductance Modeling”. DATE 2000 [2] Devgan, A., Ji, H., and Dai, W. “How to efficiently capture on-chip inductance effects: introducing a new circuit element K”. International Conference on Computer Aided Design, 2000. [3] Yin, L and He, L. “An efficient analytical model of coupled on-chip RLC interconnects”. In Proceedings of the 2001 Asia and South Pacific Design Automation Conference (Yokohama, Japan). ASP-DAC 2001

Inductance is a long-range effect Conclusions Inductance is a long-range effect Inductance can be extracted efficiently use PEEC model Normalized RLC circuit model with a much reduced complexity can be used for buses Full RLC circuit model should be used for random nets, and sparse inductance model may reduce circuit complexity

Outline Capacitance Extraction Introduction Table based method Formula based method Inductance Extraction RLC circuit model generation RLC circuit model Inductance screening Finite element method (FEM) based Extraction frequency-independent RC Frequency-dependent resistance and inductance Homework

Overview of FEM Boundary Value Problem Piece-wise Polynomial Approximation Essence of FEM: Piece-wise approximation of a function by means of polynomials each defined over a small element and expressed as nodal values of the function.

FEM – Collocation method BVP Approximation on residual form Collocation method Select m collocation points Let the residual be zero at these points.

FEM - basis Principal Attraction: Approximation solutions can be found for problems that cannot otherwise be solved, e.g., there is no closed form, or analytical solution. FEM Advantages: Applicable to any field problem. No geometric restriction. Boundary conditions not restricted. Approximation is easily improved with more refined mesh.

FEM based Extraction Flow 3-D Capacitance extraction using FEM [FastCap, MIT92] Discretization of the charge on the surface of each conductor. (charge distributed evenly on each panel) Assign excitation voltage to one conductor at a time Form linear system P·q=v P – potential coefficient matrix q – charge vector v – potential vector Solve P·q=v for charge q on all conductor panels. Charge on excited conductor gives self capacitance. Charge on other conductors gives mutual capacitance.

FEM based Extraction Flow 3-D Inductance Extraction using FEM [fasthenry, MIT94] Partition conductor into filaments (current distributed evenly) Ib is the current vector of b filaments Vb is the branch voltage vector. R is a diagonal matrix of filament dc resistances. L is a matrix of partial inductance; li is a unit vector along the length of filament i; ai is the cross section area; Vi and V’j are the volumes of filaments i and j, respectively.

FEM based Extraction Flow M – mesh matrix Im – vector of mesh currents at mesh loops. Vs – vector of source branch voltages. Set voltage source Vs1 Solve for the entries of Im associated with the source branches. With voltage Vs1 and current Is1 at terminal of conductor, the impedance can be obtained:

Inductance Calculation – from filament to wire In order to catch the frequency-dependence, a wire can be divided into filaments, where current is assumed to be uniform in filaments. For each filament, formulae can be used to get Self-inductance Mutual-inductance between it with any other filament. Problem: how to get wire inductance with those of filaments?

Inductance Calculation – from filament to wire Assume conductor Tk has P filaments, and Tm has Q filaments Mutual Inductance Self Inductance If k=m, Lpkm is the self Lp for one conductor Lpkm is the mutual inductance between conductor Tk and Tm Lpij is the mutual inductance between filament i of Tk and filament j of Tm

Reading Assignment [1] K. Nabors and J. White, FastCap: A multipole accelerated 3-D capacitance extraction program, IEEE Trans. Computer-Aided Design, 10(11): 1447-1459, 1991. [2] W. Shi, J. Liu, N. Kakani and T. Yu, A fast hierarchical algorithm for three-dimensional capacitance extraction, IEEE Trans. CAD, 21(3): 330-336, 2002 [3] M. Kamon, M. J. Tsuk, and J. K. White, “Fasthenry: a multipole-accelerated 3-D inductance extraction program,” IEEE Trans. Microwave Theory Tech., pp. 1750 - 1758, Sep 1994. [4] http://www.rle.mit.edu/cpg/research_codes.htm (FastCap, FastHenry, FastImp)

Homework (due April 15) (1) Given three wires, each modeled by at least 2 filaments, find the 3x3 matrix for (frequency-independent) inductance between the 3 wires. (2) Build the RC and RCL circuit models in SPICE netlist for the above wires. We assume that the ground plane has infinite size and is 10 um away for the purpose of capacitance calculation. (hint, use a matlab code to generate matrix and SPICE netlist) (3) Assume a step function applied at end-end, compare the four waveforms at the far-end for the central wire using SPICE transient analysis for (a) RC and RLC models and (b) rising time is 10ps and 10ns, respectively. W=4um, T=2um, l=60um, H=10um, Copper conductor:ρ = 0.0175mm2/m (room temperature), µ =1.256×10−6H/m, free space 0=8.85×10 -12F/m T l S W H

Discretization and L calculation Discretize 3 wires into 6 filaments. Step 1 Filament 6 Filament 1 T l S W Discretization and L calculation Discretize 3 wires into 6 filaments. For each filament, calculate its self-inductance with (e.g.) For each pair of filament, calculate the mutual inductance with (e.g.) Different filaments and formulae may be used for better accuracy.

Step 2 Calculate inductance matrix of three wires Mutual Inductance Self Inductance If k=m, Lpkm is the self Lp for one conductor T l S W Lpkm is the mutual inductance between conductor Tk and Tm Lpij is the mutual inductance between filament i of Tk and filament j of Tm

Capacitance Calculation Step 3 Capacitance Calculation C1 C2 C3 C4 C5 C1 and C5 equals to average of those for the following two cases: single wire over ground three parallel wires over ground Total cap below needs to be split into ground and coupling cap

Step 4 Resistance Calculation ρ = 0.0175mm2/m l is length of wire A is area of wire’s cross section Generate RC and RCL net-list for SPICE simulator. Compare their waveforms Suggested Input: VDD 1 0 PULSE(0 1 0 10ps) Output volt 1 10ps 50ps time Input

Accurate result C1 C2 C3 C4 C5 L matrix (three wires; Unit: H) Capacitance (F) C1 C2 C3 C4 C5 C1 C2 C3 C4 C5 2.8e-12 2.28e-14 1.3e-13 2.28e-14 2.8e-12

Waveform from different models RC model RLC model