STATUS OF SKIROC and ECAL FE PCB 24 November, 2018

Julien Fleury - SKIROC ASIC and PCB status - Calice Meeting, Pragua Plan ECAL : Skiroc presentation A brief reminder Measurement has started Working features A MIP in Skiroc PCB R&D What we have in hand The ASU PCB Schedule & conclusion 24 November, 2018 Julien Fleury - SKIROC ASIC and PCB status - Calice Meeting, Pragua

Julien Fleury - SKIROC ASIC and PCB status - Calice Meeting, Pragua SKIROC STATUS 24 November, 2018 Julien Fleury - SKIROC ASIC and PCB status - Calice Meeting, Pragua

Reminder : Block scheme of SKIROC Analog channel Analog mem. 36-channel Wilkinson ADC Event builder Main Memory SRAM Ch. 0 Analog channel Analog mem. Ch. 1 ECAL SLAB Analog channel Analog mem. Ch. 35 24 bit counter Time digital mem. Bunch crossing Com module Trigger control Memory pointer 24 November, 2018 Julien Fleury - SKIROC ASIC and PCB status - Calice Meeting, Pragua

Reminder : One channel 20M 1M 200ns G=10 G=1 Analog Memory Depth = 5 12 bits ADC Gain selection 0=>6pF 3-bit threshold adjustment 10-bit DAC Common to the 36Channels T 100ns DAC output Q HOLD Preamp Ampli Slow Shaper Fast Shaper Trigger Charge measurement 3pF Calibration input input 24 November, 2018 Julien Fleury - SKIROC ASIC and PCB status - Calice Meeting, Pragua

SKIROC : tested features Preamplifier Preamp disable (DC coupled channel OFF – leakage to supply) Preamp low Rf (DC coupled degrated mode) Auto-trigger Self trigger on a MIP observed in measurement Power pulsing Programmable stage by stage Calibration injection capacitance Embedded bandgap for references Embedded DAC for trig threshold Serial analogue output Probe bus for debug 24 November, 2018 Julien Fleury - SKIROC ASIC and PCB status - Calice Meeting, Pragua

Julien Fleury - SKIROC ASIC and PCB status - Calice Meeting, Pragua First measurement Before any quantitative measurement, some qualitative results to get courage ! 1 MIP in SKIROC Charge measurement Self trigger 24 November, 2018 Julien Fleury - SKIROC ASIC and PCB status - Calice Meeting, Pragua

Julien Fleury - SKIROC ASIC and PCB status - Calice Meeting, Pragua Pedestal dispersion The pedestal measurement is coherent with what we expect : No pedestal pattern (random values according to statistical dispersion) Statistical dispersion equivalent to what we get with that technology Standard deviation : σGain 1= 1.8mV σGain 10= 1.95mV 24 November, 2018 Julien Fleury - SKIROC ASIC and PCB status - Calice Meeting, Pragua

SKIROC : test to be performed Dynamic range Noise Trigger efficiency Linearity Stability Crosstalk DAC resolution ADC resolution Power pulsing & consumption DC coupling capability (leakage current swallowing) SInce we have debugged the chip control, these tests will be performed ASAP 24 November, 2018 Julien Fleury - SKIROC ASIC and PCB status - Calice Meeting, Pragua

Julien Fleury - SKIROC ASIC and PCB status - Calice Meeting, Pragua ECAL PCB STATUS 24 November, 2018 Julien Fleury - SKIROC ASIC and PCB status - Calice Meeting, Pragua

What we have in hand : stitch-test Stitchable PCB : - Designed only for mechanical and feasibility study 1*1 cm² pads 6*6 cm² wafers Still a lot of work on « stitching techniques » 24 November, 2018 Julien Fleury - SKIROC ASIC and PCB status - Calice Meeting, Pragua

What we have in hand : FEV4 Physics prototype PCB - Designed to validate the chip embedding 1*1 cm² pads 6*6 cm² wafers Only one wafer active (36 ch.) Under test (ie still not working) No probe and no pintest ! 24 November, 2018 Julien Fleury - SKIROC ASIC and PCB status - Calice Meeting, Pragua

FLC_FEV5 presentation SPIROC HARDROC 18cm PCB WAFER 18cm 1296 channels. Half SPIROC (18 chips) / half HARDROC (12 chips) 24 November, 2018 Julien Fleury - SKIROC ASIC and PCB status - Calice Meeting, Pragua

High voltage distribution AC coupling : Amp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 -200V 1 Wafer 1 Channel DC coupling : Amp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 200V 200V 1 Wafer 1 Channel 24 November, 2018 Julien Fleury - SKIROC ASIC and PCB status - Calice Meeting, Pragua

Solution for HV decoupling N high-voltage lines, suppliing 1/N of the total number of wafer + decoupling Ground return through PCB Decoupling with parasitic capacitance of other channels Amp FEE : DC coupled Nb of channel/HV line > 1000  Crosstalk < 1/1000 24 November, 2018 Julien Fleury - SKIROC ASIC and PCB status - Calice Meeting, Pragua

Julien Fleury - SKIROC ASIC and PCB status - Calice Meeting, Pragua PCB design schedule Schedule ASICs production to be started in summer 2008 ASICs have to be tested on PCB to validate daisy-chain « communication module » is the same for the three chips : SKIROC (ECAL) HARDROC (DHCAL) SPIROC (AHCAL) Roughly : PCB R&D finishes when ASIC production starts Ready to assemble Module assembled Chip production 2007 2008 2009 24 November, 2018 Julien Fleury - SKIROC ASIC and PCB status - Calice Meeting, Pragua

Julien Fleury - SKIROC ASIC and PCB status - Calice Meeting, Pragua Conclusion Less than one year to finish the EUDET module design All interface have to be defined very soon WAFER Mechanic DIF ASIC FE-PCB 24 November, 2018 Julien Fleury - SKIROC ASIC and PCB status - Calice Meeting, Pragua