ECE 448: Lab 6 Using PicoBlaze Fast Sorting Class Exercise 2.

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Presentation transcript:

ECE 448: Lab 6 Using PicoBlaze Fast Sorting Class Exercise 2

Agenda for today Introduction to Lab 6 Exercise 2 Lab 5 Demos

Introduction to Lab 6 Exercise 2 ECE 448 – FPGA and ASIC Design with VHDL

Sources P. Chu, FPGA Prototyping by VHDL Examples Chapter 14, Picoblaze Overview Chapter 15, Picoblaze Assembly Code Development Chapter 16, Picoblaze I/O Interface Chapter 17, Picoblaze Interrupt Interface K. Chapman, PicoBlaze for Spartan-6, Virtex-6, 7-Series, Zynq and UltraScale Devices (KCPSM6)) ECE 448 – FPGA and ASIC Design with VHDL

Lab Exercise 2 Finding a Maximum Element in the array of 255 pseudorandom numbers stored in Data RAM External RAM The following subroutines are used to initialize the Memories (Data RAM and External RAM) init_rand1 init_rand2 (Given on the webpage) These Subroutines generate 255 pseudorandom numbers based on an 8 bit LFSR

The initial state of LFSR is assumed to be R7..0 = 0x75 8-bit LFSR The initial state of LFSR is assumed to be R7..0 = 0x75

Task 1 Write a program that finds a location of the maximum value stored in the Data RAM after running init_rand1 The value of this location should be then written to the external register led

Task 1 - Subtasks Debug, verify, and demonstrate the operation of your program using FIDEx IDE Generate the code of Instruction RAM Describe a top-level circuit, shown in the diagram on the previous slide, using VHDL Prepare a UCF file in which you associate outputs of the register led with the pins of Spartan-6/Artix-7 connected to 8 LEDs of Nexys 3/Nexys 4 Implement the entire circuit using FPGA tools, and verify its operation using Nexys 3/Nexys 4

Task 2 Modify the program developed in Task 1, so it finds a location of the maximum value stored in External Memory after running the subroutine init_rand2 The value of this location should be then written to the external register led Assume that all numbers stored in External RAM are 8-bit unsigned integers

Task 2 - Subtasks Design the “decoding circuit” shown in the diagram. This circuit should generate the control signals led_en and RAM_en, based on the values of write_strobe and port_id. Assume that the register led is visible under the I/O address 0xFF and EXT RAM is visible under the address range 0x00..0xFE. Generate the code of Instruction RAM. Describe a top-level circuit, shown in the diagram on the previous slide, using VHDL. Simulate, verify, and demonstrate the operation of this circuit using ISim. Implement the top-level circuit using FPGA tools, and verify its operation using Nexys 3/Nexys 4. Use the UCF file developed in Task 1.

Lab 5 Demos ECE 448 – FPGA and ASIC Design with VHDL