Day 26: November 1, 2013 Synchronous Circuits ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 26: November 1, 2013 Synchronous Circuits Penn ESE370 Fall2013 -- DeHon

Today Clocking Timing discipline Latches Registers Penn ESE370 Fall2013 -- DeHon

Accumulator Consider an accumulator based on your 16b adder: What can change the observed delay of this accumulator? Penn ESE370 Fall2013 -- DeHon

Challenge Logic paths have different delays E.g. different output bits in an adder Delay of signal data dependent E.g. length of carry Delay is chip dependent E.g. Threshold Variation Delay is environment dependent E.g. Temperature Penn ESE370 Fall2013 -- DeHon

Challenge Logic paths have different delays Delay of signal data dependent Delay is chip dependent Delay is environment dependent Proper behavior depends on inputs being coordinated Match the inputs that should interact Penn ESE370 Fall2013 -- DeHon

Accumulator Consider an accumulator based on your 16b adder: What timing property must hold for this to function correctly? Penn ESE370 Fall2013 -- DeHon

Accumulator Why don’t we have to worry about: Result coming out too early? (too fast?) The accumulation bits change at different times? Penn ESE370 Fall2013 -- DeHon

Discipline Add circuit elements to hold values and change at coordinated point Control when changes seen by circuit Only have to make sure to wait long enough for all results Decouple timing of signal change from timing of signal usage Penn ESE370 Fall2013 -- DeHon

Register Use Where do we commonly use registers in our circuits? Penn ESE370 Fall2013 -- DeHon

Synchronous Discipline Add state elements (registers, latches) Compute From state elements Through combinational logic To new values for state elements Penn ESE370 Fall2013 -- DeHon

What does this do? Penn ESE370 Fall2013 -- DeHon

Latch f=0  Out=In f=1  Out=Out f transitions 01 Out holds value Penn ESE370 Fall2013 -- DeHon

Latch In pass-through mode (f=0), In latch mode (f=1), acts like buffer In latch mode (f=1), holds last value given Penn ESE370 Fall2013 -- DeHon

Latch In pass-through mode (f=0), In latch mode (f=1), acts like buffer In latch mode (f=1), holds last value given Ideally: on 01 transition of f snapshots value Penn ESE370 Fall2013 -- DeHon

Latch In pass-through mode (f=0), In latch mode (f=1), acts like buffer In latch mode (f=1), holds last value given Ideally: on 01 transition of f snapshots value What timing relations must hold between In and f for this behavior to occur? Penn ESE370 Fall2013 -- DeHon

Latch Timing Ideally: on 01 transition of f snapshots value What timing relations must hold between In and f for this behavior to occur? Can f transition simultaneous with In? Can In transition slightly before f ? Can In transition slightly after f ? Penn ESE370 Fall2013 -- DeHon

f=0 In=0 Node values? Penn ESE370 Fall2013 -- DeHon

T=0 both transition to 1 f=01 In=01 Node waveforms (preclass 2) Example shows a glitch that potentially oscillates Assuming all nice 0’s and 1’s Talked about may be degraded values not 0’s and 1’s (may be low pass filtered out). May or may not oscillate….metastable. Lots of good nuance and discussion not in slides Penn ESE370 Fall2013 -- DeHon

In transitions t after f? What happens to waveform? Penn ESE370 Fall2013 -- DeHon

In transitions t before f? What happens to waveform? Penn ESE370 Fall2013 -- DeHon

Latch Timing Must present input value sufficiently before the f transitions 01 Must have time to propagate and charge Out About how long is that in this case? Setup Time (tsu) – must setup latch input prior to passhold transition Penn ESE370 Fall2013 -- DeHon

Latch Timing Must not change input before switched over to hold state How long in this case? Takes time for inverter to charge before hold path enabled. Penn ESE370 Fall2013 -- DeHon

Latch Timing Must not change input before switched over to hold state Hold Time (thold)– must hold data input until passhold transition complete Penn ESE370 Fall2013 -- DeHon

Midterm 2 Topics Sizing Logic Tau-model Elmore-delay Estimation and optimization Elmore-delay Energy and power Dynamic and static Logic CMOS Ratioed Pass transistor Regions of operation Scaling Noise Margins No clocking Except to motivate delay targets and power calculations Penn ESE370 Fall2012 -- DeHon

What happens here? Penn ESE370 Fall2013 -- DeHon

Observe Latch alone In flow-through mode half of cycle Can still get flow-through, combinational cycles Penn ESE370 Fall2013 -- DeHon

Multiple Latch Discipline Open latches at disjoint times At all times: one latch on every path is closed Penn ESE370 Fall2013 -- DeHon

Register Two back-to-back latches Open one latch at a time Having one of each on every cycle breaks up combinational cycle Penn ESE370 Fall2013 -- DeHon

Register Passhold on input latch samples value Holdpass on output latch presents stored value to circuit Master and Slave latches Penn ESE370 Fall2013 -- DeHon

Register How long from f1 fall to output? Part of clkoutput (tclk-q) Penn ESE370 Fall2013 -- DeHon

What does this do? Penn ESE370 Fall2013 -- DeHon

What does this do? Outputs when Can ever both be low? Input 0? Input 1? Can ever both be low? What does output waveform look like? Penn ESE370 Fall2013 -- DeHon

Clocking Discipline Identify: setup, hold, clk->Q, logic evaluation Penn ESE370 Fall2013 -- DeHon

Clocking Discipline Penn ESE370 Fall2013 -- DeHon

Clocking Discipline Follow discipline of combinational logic broken by registers Compute From state elements Through combinational logic To new values for state elements As long as clock cycle long enough, Will get correct behavior Penn ESE370 Fall2013 -- DeHon

Ideas Synchronize circuits Leads to clocked circuit discipline to external events disciplined reuse of circuitry Leads to clocked circuit discipline Uses state holding element Prevents Combinational loops Timing assumptions (More) complex reasoning about all possible timings Penn ESE370 Fall2013 -- DeHon

Admin Exam Monday Daylight savings time ends Sunday 2am No class at noon – office hour Exam 7—9pm in Towne 309 Daylight savings time ends Sunday 2am Get an extra hour to study for exam! Review Sunday 3pm, Ketterer (make sure you account for time change!) Penn ESE370 Fall2013 -- DeHon