Introduction to CMOS VLSI Design Chapter 3: CMOS Processing Technology

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Introduction to CMOS VLSI Design Chapter 3: CMOS Processing Technology This work is protected by Canadian copyright laws and is provided solely for the use of instructors in teaching their courses and assessing student learning. Dissemination or sale of any part of this work (including on the Internet) will destroy the integrity of the work and is not permitted. The copyright holder grants permission to instructors who have adopted the textbook accompanying this work to post this material online only if the use of the website is restricted by access codes to students in the instructor's class that is using the textbook and provided the reproduced material bears this copyright notice. slides from David Harris adapted by Duncan Elliott Textbook: CMOS VLSI Design - A Circuits and Design Perspective, 4th Edition, N. H. E. Weste & D. Harris Ch 3 IC Process

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Optical Proximity Correction (OPC) Masks Ch 3 IC Process

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Hot Carriers Electric fields across channel impart high energies to some carriers These “hot” carriers may be blasted into the gate oxide where they become trapped Accumulation of charge in oxide causes shift in Vt over time Eventually Vt shifts too far for devices to operate correctly Choose VDD to achieve reasonable product lifetime Worst problems for inverters and NORs with slow input risetime and long propagation delays Use lightly doped drains (LLD) to reduce hot carrier injection (HCI) Ch 3 IC Process

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Local Interconnect Ch 3 IC Process

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11 layers of metal [IBM] Ch 3 IC Process

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Ch7 Robustness & Reliability Ch 3 IC Process

Reliability Hard Errors Soft Errors Ch 3 IC Process

Electromigration “Electron wind” causes movement of metal atoms along wires Excessive electromigration leads to open circuits Most significant for unidirectional (DC) current Depends on current density Jdc (current / area) Exponential dependence on temperature Mean Time to Failure (MTTF) Typical limits: Jdc < 1 – 2 mA / mm2 Ch 3 IC Process

Self-Heating Current through wire resistance generates heat Oxide surrounding wires is a thermal insulator Heat tends to build up in wires Hotter wires are more resistive, slower Self-heating limits AC current densities for reliability Typical limits: Jrms < 15 mA / mm2 Ch 3 IC Process

Latchup Latchup: positive feedback leading to VDD – GND short Major problem for 1970’s CMOS processes before it was well understood Avoid by minimizing resistance of body to GND / VDD Use plenty of substrate and well taps Ch 3 IC Process

Guard Rings Latchup risk greatest when diffusion-to-substrate diodes could become forward-biased Surround sensitive region with guard ring to collect injected charge Ch 3 IC Process

Overvoltage High voltages can damage transistors Electrostatic discharge Oxide arcing Punchthrough Time-dependent dielectric breakdown (TDDB) Accumulated wear from tunneling currents Requires low VDD for thin oxides and short channels Use ESD protection structures where chip meets real world Ch 3 IC Process

Soft Errors In 1970’s, DRAMs were observed to occasionally flip bits for no apparent reason Ultimately linked to alpha particles and cosmic rays Collisions with particles create electron-hole pairs in substrate These carriers are collected on dynamic nodes, disturbing the voltage Minimize soft errors by having plenty of charge on dynamic nodes Tolerate errors through ECC, redundancy Ch 3 IC Process

Pitfalls Summary Static CMOS gates are very robust Will settle to correct value if you wait long enough Other circuits suffer from a variety of pitfalls Tradeoff between performance & robustness Very important to check circuits for pitfalls For large chips, you need an automatic checker. Design rules aren’t worth the paper they are printed on unless you back them up with a tool. Ch 3 IC Process