Basic Logic Gates and Truth Tables NOT (Inverter) F = A.B NAND AND F = A+B F = A+B OR NOR

Basic Logic Gates and Truth Tables

Introduction to Field Programmable Gate Arrays

Introduction to Field Programmable Gate Arrays The first FPGAs for Xilinx in 1985 using a very mature 1.2m process consists of 1,000 ASIC gate equivalent running at 18MHZ. https://anysilicon.com/fpga-vs-asic-choose/

Introduction to Field Programmable Gate Arrays

FPGA Design Flow Overview The ISE® design flow comprises the following steps: design entry, design synthesis, design implementation, and Xilinx® device programming. Design verification, which includes both functional verification and timing verification, takes places at different points during the design flow. This section describes what to do during each step. For additional details on each design step, click on a link below the following figure. https://www.xilinx.com/support/documentation/sw_manuals/xilinx10/isehelp/ise_c_fpga_design_flow_overview.htm

difference between logical and bit-wise operator Suppose A=3′b101,B=3′b010. Logical AND:- Y=A&&B means if A is true(non-zero) and B(non-zero) is true Y will get ‘1’ else ‘0′. So here Y=1. Bit-wise AND:- Y=A&B means bit-wise and operation of A,B. So here Y=3′b000. Logical OR:- Y=A||B means if any of these two true i.e. A is true(non-zero) or B(non-zero) is true Y will get ‘1’ else if both are false(Zero) then ‘0′. So here Y=1; Bit-wise OR:- Y=A|B means bit-wise ‘or’ operation of A,B. So here Y=3′b111. But the trick is with NOT operation. Logical NOT:- Y=!B means if B is true(non-zero) Y will get false i.e. ‘0’ else ‘1′. So here Y=0. Bit-wise NOT:- Y=~B means bit-wise complement operation of B. So here Y=3′b101.

== tests for only 1 and 0, Precedence of Operations in Verilog Verilog HDL operators can be divided into several groups Highest Lowest == tests for only 1 and 0, while === tests for 1, 0, X, Z.

1 1 1 Q1Q0 1/1 Current St Q1Q0 Input In Next St Q1+Q0+ Output Out 0 0 0 1 1 1 0 1 1 In 00 01 11 10 00 0/1 01 1 1 1/0 0/0 Q1+ = Q1’Q0 + Q1Q0’ 1/1 0/1 1/1 Q1Q0 In 11 0/0 10 00 01 11 10 1 1 Q0+ = In’Q0’ + In’Q1 + InQ1’Q0 Q1’Q0 + Q1Q0’ 1 Q1Q0 In 00 01 11 10 CLK 1 1 1 Out = InQ0 + Q1’Q0’ + Q1Q0 In’Q0’ + In’Q1 + InQ1’Q0 Out = InQ0 + Q1’Q0’ + Q1Q0

Examples to complete two_input_xor: assign out = in1 ^ in2; // example 2 wire product1, product2; assign product1 = in1 && !in2; // could have done in assign product2 = !in1 && in2; // single assignment assign out = product1 || product2; // statement… // example 3 assign out = (in1 != in2); // example 4 assign out = in1 ? (!in2) : (in2);

// Behavioral Model of a 4 to 1 MUX (16 data inputs) module mux_4to1(Y, A, B, C, D, sel); output [15:0] Y; input [15:0] A, B, C, D; input [1:0] sel; reg [15:0] Y; always @(A or B or C or D or sel) case ( sel ) 2'b00: Y = A; 2'b01: Y = B; 2'b10: Y = C; 2'b11: Y = D; default: Y = 16'hxxxx; endcase endmodule // Behavioral Model of a 2 to 1 MUX (16 data inputs) module mux_2to1(Y, A, B, sel); output [15:0] Y; input [15:0] A, B; input sel; reg [15:0] Y; always @(A or B or sel) if (sel == 1'b0) Y = A; else Y = B; endmodule

2-bit MUX examples Using if Statement Using case Statement Using assign Statement http://www.asic-world.com/examples/verilog/mux.html

http://euler.ecs.umass.edu/ece232/pdf/03-verilog-11.pdf

Sample Test Questions

Synthesis of Combinational Logic – Gate Netlist Synthesis tools further optimize a gate netlist in term of Verilog primitives. Example: Given the pre-synthesized circuit below, write the Verilog, optimize circuit using only 2-input gates (Optimized) cs.haifa.ac.il/courses/verilog/verilog_tutorial2.ppt

http://www. syssec. ethz http://www.syssec.ethz.ch/content/dam/ethz/special-interest/infk/inst-infsec/system-security-group-dam/education/Digitaltechnik_14/07_Verilog_Combinational.pdf

Structural Modeling of Sequential Circuits // Mixed Structural and Dataflow module Seq_Circuit_Structure (input In, CLK, output Out); wire D0, D1, Q0, Q0b, Q1, Q1b; // Instantiate two D Flip-Flops D_FF FF0(D0, CLK, Q0, Q0b); D_FF FF1(D1, CLK, Q1, Q1b); // Modeling logic assign D0 = Q1b & In; assign D1 = (Q0 & ~In) | (Q1 & ~In); assign Out = Q0 & Q1; endmodule