HDL Compiler Unsupport (Do NOT use in your verilog code)

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Presentation transcript:

HDL Compiler Unsupport (Do NOT use in your verilog code) delay (# will ignore) initial ( add a reset signal ) repeat wait fork event deassign force release

Synthesisable HDL coding always @(posedge a) out = in1; always @(posedge b) out = in2; Warning! Synthesized function will go wrong *Can not assign identical reg in more than one blocks

Conbinational Logic always @(sel) if (sel==1) out = in1; else *Warning !! in1 1 out in2 always @(sel or in1 or in2) if (sel==1) out = in1; else out = in2; sel Multiplexer

Register always @(posedge clk or posedge reset) if ( reset ) out=0; else out= a & b; Register with asynchronize reset always @(posedge clk) if ( reset ) out=0; else out= a & b; Register with synchronize reset

Latch always @(sel or in) if (sel==1) out = in; Incomplete if statement always @(sel or in) case ( sel ) 2’b00: out=in1; 2’b01: out=in2; 2’b10: out=in3; endcase Not a full case

Finite State Machine Combinational logic next_state generator always @(current_state or data1 or data2) case ( current_state ) S0: begin result=data1; next_state=S1; end S1: ....... endcase Combinational logic next_state generator always @(posedge clk) if ( reset ) current_state=S0; else current_state=next_state; Sequential logic state transition