EE 435 Spring 2013 http://class.ece.iastate.edu/djchen/ee435/2013 Lecture 1 Course Outline

Instructors Lecture Instructor: Laboratory Instructor: Degang Chen Office: 2134 Coover Hall VoicePhone: 294-6277 Email: djchen@iastate.edu Laboratory Instructor: Rui Bai Office: 3102 Coover Hall Voice Phone: 515-509-5457 Email:  bairui@iastate.edu Kossi Sessou Email: serkkom@iastate.edu

Poll on time availability A one-hour slot Group office hour Supplementary help session Make-up lectures Section C lab time R12:30-3:00 Other?

Analog Integrated Circuit Design Course Information: Required Text: Analog Integrated Circuit Design by T. Carusone, D. Johns and K. Martin, Wiley, 2011 Errata: http://analogicdesign.com/students/errata/ Focus materials: Amplifier design: Chapters 3, 4, 5, 6 Data converter: Chapters 15, 16, 17 Other materials: Noise, references, comparators Chapters 7, 9, 10

Course Information: Reference Texts: CMOS Analog Circuit Design, 3rd Edition by Allen and Holberg, Oxford, 2012 Analysis and Design of Analog Integrated Circuits-5th Edition Gray,Hurst,Lewis and Meyer, Wiley, 2009

Course Information: Reference Materials:

Catalog Description E E 435. Analog VLSI Circuit Design. (Same as Cpr E 435.) (3-3) Cr. 4. S. Prereq: 324, 330, 332, and either EE 322 or Stat 330. Basic analog integrated circuit and system design including design space exploration, performance enhancement strategies, operational amplifiers, references, integrated filters, and data converters. Non-major graduate credit.

Course Coverage by Topics Current mirrors and basic amplifiers Operational amplifier design and compensation Comparator design Voltage references Noise analysis Switches Nyquist rate D/A and A/D converters

Relation to Grad Level Courses EE501: CMOS analog IC design (operational amplifier design) EE505: Data Converter Design EE506: phase locked loops EE507: VLSI Communication Circuits EE508: Integrated Filter Design EE504: power management EE509: analog and mixed-signal testing and built-in self-test EE514: RF and Microwave Circuits, low noise amplifiers

Grading Homework: 15% Midterm Exam: 15~20% Final Exam: 30~35% Lab and Lab Reports: 10% Project 1 Report: 10% Project 2 Report: 15%

Laboratory There will be weekly laboratory experiments. The laboratory will be either on electronic measurements or on VLSI CAD design and simulation. A written report after each topic is completed

Design Projects Everyone will design a two-stage op amp Teams will design various digital to analog converters or analog to digital converters Additional details will be given after relevant material is covered in class. The option will exist to have these projects fabricated through the MOSIS program.

Disability Accommodations If you have a disability and require accommodations, please contact the instructor early in the semester so that your learning needs may be appropriately met. You will need to provide documentation of your disability to the Disability Resources (DR) office, located at 1076 Student Services Building, Ames, Iowa 50011, (515) 294-7220 http://www.dso.iastate.edu/dr/student/

Discrimination and Harassment Discrimination and harassment impede the realization of Iowa State University's mission of distinction in education, scholarship, and service, and diminish the whole community. The University is committed to provide a professional working and learning environment that is fair and responsible; that supports, nurtures, and rewards educational growth on the basis of relevant factors such as ability and performance; and that is free of discriminatory, inappropriate, and disrespectful conduct or communication. In this class, we are committed to maintain an atmosphere that is free from prohibited discrimination and harassment based upon race, ethnicity, sex, pregnancy, color, religion, national origin, physical or mental disability, age, marital status, sexual orientation, status as a U.S. veteran, or any other status protected by law. For more information regarding Iowa State University policy and procedures, please visit http://policy.iastate.edu/policy/discrimination/.

Additional Comments E-mail communication is strongly encouraged Personal visit to my office is also encouraged Either academic or non-academic Anytime is OK Classroom participation is strongly encouraged I prefer an interactive class I feel nervous when the class is too quiet So, do me a favor and ask questions and answer questions

First week lab Electronic measurements Extra Cadence simulation lab Required for everybody Finish in one week Report due at beginning of lab in second week Extra Cadence simulation lab Not required for people with B or better in EE330 Show simulation results to any instructor