Overview Last Lecture Conversion of two-level logic to NAND or NOR forms Multilevel logic AOI and OAI gates Today Timing and hazards Multiplexers and demultiplexers 11/27/2018 CSE 370 – Winter 2002 - Hazards - 1

Time behavior of combinational networks Waveforms visualization of values carried on signal wires over time useful in explaining sequences of events (changes in value) Simulation tools are used to create these waveforms input to the simulator includes gates and their connections input stimulus, that is, input signal waveforms Some terms gate delay — time for change at input to cause change at output min delay – typical/nominal delay – max delay careful designers design for the worst case rise time — time for output to transition from low to high voltage fall time — time for output to transition from high to low voltage pulse width — time that an output stays high or stays low between changes 11/27/2018 CSE 370 – Winter 2002 - Hazards - 2

Momentary changes in outputs Can be useful — pulse shaping circuits Can be a problem — incorrect circuit operation (glitches/hazards) Example: pulse shaping circuit A' • A = 0 delays matter in function F A B C D D remains high for three gate delays after A changes from low to high F is not always 0 pulse 3 gate-delays wide 11/27/2018 CSE 370 – Winter 2002 - Hazards - 3

Oscillatory behavior Another pulse shaping circuit NOT combinational logic! switch is close: steady state switch is open: oscillation + open switch resistor A B C D close switch initially undefined open switch 11/27/2018 CSE 370 – Winter 2002 - Hazards - 4

Hazards/glitches Hazards/glitches: unwanted switching at the outputs occur when different paths through circuit have different propagation delays as in pulse shaping circuits we just analyzed dangerous if logic causes an action while output is unstable may need to guarantee absence of glitches Usual solutions 1) wait until signals are stable (by using a clock) preferable (easiest to design when there is a clock – synchronous design) 2) design hazard-free circuits sometimes necessary (clock not used – asynchronous design) 11/27/2018 CSE 370 – Winter 2002 - Hazards - 5

Types of hazards Static 1-hazard 1 input change causes output to go from 1 to 0 to 1 Static 0-hazard input change causes output to go from 0 to 1 to 0 Dynamic hazards input change causes a double change from 0 to 1 to 0 to 1 OR from 1 to 0 to 1 to 0 1 1 1 1 11/27/2018 CSE 370 – Winter 2002 - Hazards - 6

Static hazards Due to a literal and its complement momentarily taking on the same value through different paths with different delays and reconverging May cause an output that should have stayed at the same value to momentarily take on the wrong value Example: A A S B S' B F S S' F hazard static-0 hazard static-1 hazard 11/27/2018 CSE 370 – Winter 2002 - Hazards - 7

Dynamic hazards Due to the same versions of a literal taking on opposite values through different paths with different delays and reconverging May cause an output that was to change value to change 3 times instead of once (outside scope of this course) Example: (assume B1 changes before B2 and B2 before B3) A C A C B F 1 2 3 B1 B2 B3 F hazard dynamic hazards 11/27/2018 CSE 370 – Winter 2002 - Hazards - 8

Eliminating static hazards (an overview) In 2-level logic assuming single-bit changes Basic idea: a static hazard happens when a changing input spans multiple prime implicants Example: 1101 change to 0101 can cause a static-1 hazard AB F = AC’ + A’D 00 01 11 10 CD A 00 01 10 11 0 0 1 1 C’ F 1 1 1 1 A’ 1 1 0 0 D 0 0 0 0 11/27/2018 CSE 370 – Winter 2002 - Hazards - 9

Eliminating static hazards (ct’d) Solution: Add redundant prime implicants Ensure that all single bit changes (adjacent 1’s) are covered by an implicant To eliminate static-1 hazard, use SOP form To eliminate static-0 hazard, use POS form AB F = AC’ + A’D +C’D 00 01 11 10 CD A 00 01 10 11 0 0 1 1 C’ 1 1 1 1 A’ 1 1 0 0 F D 0 0 0 0 C’ D 11/27/2018 CSE 370 – Winter 2002 - Hazards - 10

Eliminating hazards (ct’d) We can eliminate static hazards in 2-level logic for: Single-bit changes (side benefit: eliminates some dynamic hazards) But, more generally, eliminating hazards is difficult Multiple-bit changes in 2-level logic are hard Static hazards in multilevel logic are harder Dynamic hazards in multiple logic are harder yet CAD tools and simulation/testing are indispensable Test vectors probe a design for hazards 11/27/2018 CSE 370 – Winter 2002 - Hazards - 11

Making connections Direct point-to-point connections between gates wires we've seen so far Route one of many inputs to a single output --- multiplexer Route a single input to one of many outputs --- demultiplexer control control multiplexer demultiplexer 11/27/2018 CSE 370 – Winter 2002 - Hazards - 12

Mux and demux Uses of multiplexers/demultiplexers in multi-point connections A0 A1 B0 B1 Sa Sb MUX MUX multiple input sources A B Sum Ss multiple output destinations DEMUX S0 S1 11/27/2018 CSE 370 – Winter 2002 - Hazards - 13

Multiplexers (aka selectors) Multiplexers/selectors: general concept 2n data inputs, n control inputs (called "selects"), 1 output used to connect 2n points to a single point control signal pattern forms binary index of input connected to output I1 I0 A Z 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 A Z 0 I0 1 I1 Z = A' I0 + A I1 A is control I0 , I1 are input Z is output functional form logical form two alternative forms for a 2:1 Mux truth table 11/27/2018 CSE 370 – Winter 2002 - Hazards - 14

Multiplexers/selectors (cont'd) 2:1 mux: Z = A' I0 + A I1 4:1 mux: Z = A' B' I0 + A' B I1 + A B' I2 + A B I3 8:1 mux: Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 + A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7 In general, Z =  (mkIk) in minterm shorthand form for a 2n:1 Mux n 2 -1 I0 I1 I2 I3 I4 I5 I6 I7 A B C 8:1 mux Z k=0 I0 I1 I2 I3 A B 4:1 mux Z I0 I1 A 2:1 mux Z 11/27/2018 CSE 370 – Winter 2002 - Hazards - 15

Gate level implementation of muxes 11/27/2018 CSE 370 – Winter 2002 - Hazards - 16