ECE 667 Synthesis and Verification of Digital Systems

Slides:



Advertisements
Similar presentations
Courtesy RK Brayton (UCB) and A Kuehlmann (Cadence) 1 Logic Synthesis Factored Forms.
Advertisements

ECE 667 Synthesis & Verification - Algebraic Division 1 ECE 667 ECE 667 Synthesis and Verification of Digital Systems Multi-level Minimization Algebraic.
ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions.
ECE 331 – Digital System Design
1 Outline Division is central in many operations. –What is it (in the context of Boolean functions)? –What to divide (divisor) with? –How to divide (quotient.
Logic Synthesis Part II
Technology Mapping.
1 Generalized Buffering of PTL Logic Stages using Boolean Division and Don’t Cares Rajesh Garg Sunil P. Khatri Department of Electrical and Computer Engineering,
Synthesis For Mixed CMOS/PTL Logic
Boolean Functions and their Representations
1 BDS: A BDD-Based Logic Optimization System “BDS: A BDD-Based Logic Optimization System”, by Congguang Yang and Maciej Ciesielski, 2000 By Chang Seok.
ECE Synthesis & Verification - Lecture 19 1 ECE 667 Spring 2009 ECE 667 Spring 2009 Synthesis and Verification of Digital Systems Functional Decomposition.
ECE Synthesis & Verification - Lecture 9b 1 ECE 697B (667) Fall 2004 ECE 697B (667) Fall 2004 Synthesis and Verification of Digital Systems Boolean.
ECE Synthesis & Verification - Lecture 14 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems BDD-based.
Taylor Expansion Diagrams (TED): Verification EC667: Synthesis and Verification of Digital Systems Spring 2011 Presented by: Sudhan.
1 Synthesis For CMOS/PTL Circuits Congguang Yang Maciej Ciesielski Dept. of Electrical & Computer Engineering University of Massachusetts, Amherst Sponsored.
ECE Synthesis & Verification - Lecture 10 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems Binary.
Logic Synthesis 3 1 Logic Synthesis Part III Maciej Ciesielski Univ. of Massachusetts Amherst, MA.
ECE 667 Synthesis & Verification - Multi-level Optimization 1 ECE 667 ECE 667 Synthesis and Verification of Digital Systems Multi-level Minimization (Kernel-based)
 2000 M. CiesielskiPTL Synthesis1 Synthesis for Pass Transistor Logic Maciej Ciesielski Dept. of Electrical & Computer Engineering University of Massachusetts,
ECE 667 Synthesis and Verification of Digital Systems
Logic Decomposition ECE1769 Jianwen Zhu (Courtesy Dennis Wu)
ECE 667 Synthesis and Verification of Digital Systems
ECE Synthesis & Verification - Lecture 8 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems Multi-level.
Lecture 4 4. Boolean functions – advanced
Computer Architecture I: Digital Design Dr. Robert D. Kent Logic Design Medium Scale Integration and Programmable Logic Devices Part I.
State university of New York at New Paltz Electrical and Computer Engineering Department Logic Synthesis Optimization Lect19: Multi Level Logic Minimization.
Combinational Problems: Unate Covering, Binate Covering, Graph Coloring and Maximum Cliques Example of application: Decomposition.
Two Level and Multi level Minimization
Multi-Level Logic Optimization. Multi-Level Logic Synthesis Two Level Logic : –Espresso –Programmable Logic Array (PLA) Multilevel Logic : –Standard Cell.
Technology Mapping. 2 Technology mapping is the phase of logic synthesis when gates are selected from a technology library to implement the circuit. Technology.
Mihir Choudhury, Kartik Mohanram (ICCAD’10 best paper nominee) Presentor: ABert Liu.
Boolean Functions 1 ECE 667 ECE 667 Synthesis and Verification of Digital Circuits Boolean Functions Basics Maciej Ciesielski Univ.
BDS – A BDD Based Logic Optimization System Presented by Nitin Prakash (ECE 667, Spring 2011)
State university of New York at New Paltz Electrical and Computer Engineering Department Logic Synthesis Optimization Lect18: Multi Level Logic Minimization.
Theory of Computational Complexity Probability and Computing Chapter Hikaru Inada Iwama and Ito lab M1.
Logic Synthesis Boolean Division.
ECE 331 – Digital System Design
ECE 301 – Digital Electronics
ECE 667 Synthesis and Verification of Digital Systems
The countable character of uncountable graphs François Laviolette Barbados 2003.
Delay Optimization using SOP Balancing
ECE 331 – Digital System Design
Faster Logic Manipulation for Large Designs
Reading: Hambley Chapters
A. Mishchenko S. Chatterjee1 R. Brayton UC Berkeley and Intel1
Basics Combinational Circuits Sequential Circuits
Reconfigurable Computing
Example of application: Decomposition
A Boolean Paradigm in Multi-Valued Logic Synthesis
ECE 667 Synthesis and Verification of Digital Systems
Propositional Calculus: Boolean Algebra and Simplification
Faster Logic Manipulation for Large Designs
ECE 667 Synthesis and Verification of Digital Circuits
EECS150 - Digital Design Lecture 7 - Boolean Algebra II
SAT-based Methods for Scalable Synthesis and Verification
Sungho Kang Yonsei University
ECE 667 Synthesis and Verification of Digital Systems
Binary Decision Diagrams
Overview Part 2 – Circuit Optimization
Technology Mapping I based on tree covering
VLSI CAD Flow: Logic Synthesis, Placement and Routing Lecture 5
ECE 352 Digital System Fundamentals
design entry (schematic capture, VHDL, truth table and etc.)
Delay Optimization using SOP Balancing
Canonical Computation without Canonical Data Structure
Illustrative Example p p Lookup Table for Digits of h g f e ) ( d c b
SAT-based Methods: Logic Synthesis and Technology Mapping
Alan Mishchenko Department of EECS UC Berkeley
Lecture 2: Combinational Logic Design
Presentation transcript:

ECE 667 Synthesis and Verification of Digital Systems BDD-based Bi-decomposition BDS system

Outline Review of current decomposition methods Algebraic Boolean Theory of BDD decomposition [C. Yang 1999] Bi-decomposition F = D  Q Boolean AND/OR Decomposition Boolean XOR Decomposition MUX Decomposition Logic optimization based on BDD decomposition ECE 667 - Synthesis & Verification - BDS

Functional Decomposition – previous work Ashenhurst [1959], Curtis [1962] Tabular method based on cut: bound/free variables BDD implementation: Lai et al. [1993, 1996], Chang et al. [1996] Stanion et al. [1995] Roth, Karp [1962] Similar to Ashenhurst, but using cubes, covers Also used by SIS Factorization based SIS, algebraic factorization using cube notation Bertacco et al. [1997], BDD-based recursive bidecomp. ECE 667 - Synthesis & Verification - BDS

Drawbacks of Traditional Synthesis Methods Weak Boolean factorization capability. Difficult to identify XOR and MUX decomposition. Separate platforms for Boolean operations and factorization. Our goal: use a common platform to carry out both Boolean operations and factorization: BDD’s ECE 667 - Synthesis & Verification - BDS

What is wrong with Algebraic Division? Divisor and quotient are orthogonal!! Better factored form might be: (q1+ q2+ …+qn) (d1+d2+…+dm) gi and dj may share same or opposite literals Example: SOP form: F = abg + acg + adf + aef + afg + bd + ce + be + cd. (23 lits) Algebraic: F = (b + c)(d + e + ag) + (d + e +g)af. (11 lits) Boolean: F = (af + b + c)(ag + d + e). (8 lits) ECE 667 - Synthesis & Verification - BDS

First work, Karplus [1988]: 1-dominator Definition: 1-dominator is a node that belongs to every path from root to terminal 1. F a b c d 1 1-dominator d 1 c a b * a + b c + d 1-dominator defines algebraic conjunctive (AND) decomposition: F = (a+b)(c+d). ECE 667 - Synthesis & Verification - BDS

Karplus: 0-dominator Definition: 0-dominator is a node that belongs to every path from root to terminal 0. a b c d 1 F 0-dominator a b 1 d c a b c d 0-dominator defines algebraic disjunctive (OR) decomposition: F = ab + cd. ECE 667 - Synthesis & Verification - BDS

Bi-decomposition based on Dominators We can generalize the concept of algebraic decomposition and dominators to: Generalized dominators Boolean bi-decompositions (AND, OR, XOR) Bi-decomposition: F = D  Q First, let’s review fundamental theorems for Boolean division and factoring. ECE 667 - Synthesis & Verification - BDS

Boolean Division Definitions Note: H and R may not be unique. G is a Boolean divisor of F if there exist H and R such that F = G H + R, and G H  0. G is said to be a factor of F if, in addition, R=0, that is: F = G H. where H is the quotient, R is the remainder. Note: H and R may not be unique. ECE 667 - Synthesis & Verification - BDS

Boolean Factor - Theorem Boolean function G is a Boolean factor of Boolean function F iff F  G , (i.e. FG’ = 0, or G’  F’). F G Proof: : G is a Boolean factor of F. Then H s.t. F = GH; Hence, F  G (as well as F  H). : F  G  F = GF = G(F + R) = GH. (Here R is any function R  G’.) Notes: - Given F and G, H is not unique. - To get a small H is the same as getting a small F + R. Since RG = 0, this is the same as minimizing (simplifying) f with DC = G’. ECE 667 - Synthesis & Verification - BDS

Boolean Division - Theorem G is a Boolean divisor of F if and only if F G  0. G F Proof: : F = GH + R, GH  0  FG = GH + GR. Since GH  0, FG  0. : Assume that FG  0. F = FG + FG’ = G(F + K) + FG’. (Here K  G’.) Then F = GH + R, with H = F + K, R = FG’. Since GH = FG  0, then GH  0. Note: f has many divisors. We are looking for a g such that f = gh + r, where g, h, r are simple functions. (simplify f with DC = g’) ECE 667 - Synthesis & Verification - BDS

Boolean Division Goal : for a given F, find D and Q such that F = Q · D. Boolean Space F D F Q F F = e + bd, D = e + d, Q = e + b ECE 667 - Synthesis & Verification - BDS

Conjunctive (AND) Decomposition Conjunctive (AND) decomposition: F = D Q. Theorem: Boolean function F has conjunctive decomposition iff F  D. For a given choice of D, the quotient Q must satisfy: F  Q  F + D’. D Q F For a given pair (F,D), this provides a recipe for Q . ECE 667 - Synthesis & Verification - BDS

Boolean Division  AND decomposition Given function F and divisor D  F, find Q such that: F  Q  F + D’. Boolean Space D’ F D F Q F F = e + bd, D = e + d, Q = e + b  F + D’ ECE 667 - Synthesis & Verification - BDS

AND Decomposition (F = D Q): Example Recall: given (F,D), quotient Q must satisfy: F  Q  F + D’. d e b 1 F = e + bd e b 1 D e b 1 D = e + b, d e b 1 DC Q d e 1 Q = e + d DC eb d 00 01 11 10 1 Q ECE 667 - Synthesis & Verification - BDS

Disjunctive (OR) Decomposition Disjunctive (OR) decomposition: F = G + H. Theorem: Boolean function F has disjunctive decomposition iff F  G. For a given choice of G, the term H must satisfy: F’  H’  F’ + G. G H F Dual to conjunctive decomposition. For a given (F,G), this provides a recipe for H . ECE 667 - Synthesis & Verification - BDS

Boolean AND/OR Bi-decompositions Conjunctive (AND) decomposition If D  F, F = F D = Q D. Disjunctive (OR) decomposition If G  F, F = F + G = H + G. D, G = generalized dominators ECE 667 - Synthesis & Verification - BDS

Generalized Dominator D f b c F 1 a f b c D 1 Boolean divisor F = D Q ECE 667 - Synthesis & Verification - BDS

Generalized Dominator G f b c F 1 a f b c G Boolean “subtractor” F = G + H ECE 667 - Synthesis & Verification - BDS

Boolean Division Based on Generalized Dominator f b c F 1 reduce a f b c D D = af + b + c 1 a f b c D 1 g d e a f b c Q 1 DC minimize g d e a Q 1 Q = ag + d + e ECE 667 - Synthesis & Verification - BDS

Special Case: 1-dominator F a b c d 1 1-dominator a b 1 a + b d 1 c * c + d F = (a+b)(c+d) ECE 667 - Synthesis & Verification - BDS

Special Case: 0-dominators b c d 1 F 0-dominator a b 1 d c a b c d F = ab + cd ECE 667 - Synthesis & Verification - BDS

Algebraic XOR Decomposition h F f f’ + = hf h’f’ = complement edge = 1-edge edge = 0-edge edge ECE 667 - Synthesis & Verification - BDS

Algebraic XOR Decomposition: x-dominators F 1 a d b c x-dominator a+b 1 a b c+d d c ECE 667 - Synthesis & Verification - BDS

Boolean XOR Decomposition: Generalized x-dominators Given F and G, there exists H : F = G  H; H = F  G. F 1 a d b c Generalized x-dominator G H ECE 667 - Synthesis & Verification - BDS

h MUX Decomposition F Simple MUX decomposition 1 v g f Complex MUX 1 Simple MUX decomposition f g h F 1 Complex MUX decomposition ECE 667 - Synthesis & Verification - BDS

Functional MUX Decomposition - example h f g 1 1 b a F d c ECE 667 - Synthesis & Verification - BDS

Synthesis Flow Boolean Network Construct Global BDDs Variable Reorder Decompose BDD Construct Factoring Trees Factoring Tree Processing Technology Mapping ECE 667 - Synthesis & Verification - BDS

Factoring Tree Processing: ECE 667 - Synthesis & Verification - BDS

A Complete Synthesis Example ECE 667 - Synthesis & Verification - BDS

A Complete Synthesis Example (Decompose function g) ECE 667 - Synthesis & Verification - BDS

A Complete Synthesis Example (Decompose function h) ECE 667 - Synthesis & Verification - BDS

A Complete Synthesis Example (Sharing Extraction) ECE 667 - Synthesis & Verification - BDS

Conclusions BDD-based bi-decomposition is a good alternative to traditional, algebraic logic optimization Produces Boolean decomposition Several types: AND, OR, XOR, MUX BDD decomposition-based logic optimization is fast. Stand-alone BDD decomposition scheme is not amenable to large circuits Global BDD too large Must partition into network of BDDs (local BDDs) ECE 667 - Synthesis & Verification - BDS