Tong Jing, Ling Zhang, Jinghong Liang

Slides:



Advertisements
Similar presentations
Group: Wilber L. Duran Duo (Steve) Liu
Advertisements

UCLA Modeling and Optimization for VLSI Layout Professor Lei He
Optimization of Placement Solutions for Routability Wen-Hao Liu, Cheng-Kok Koh, and Yih-Lang Li DAC’13.
Wen-Hao Liu1, Yih-Lang Li, and Cheng-Kok Koh Department of Computer Science, National Chiao-Tung University School of Electrical and Computer Engineering,
Meng-Kai Hsu, Sheng Chou, Tzu-Hen Lin, and Yao-Wen Chang Electronics Engineering, National Taiwan University Routability Driven Analytical Placement for.
1 Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Buffer Insertion Presented By Cesare Ferri Takumi Okamoto, Jason Kong.
Ripple: An Effective Routability-Driven Placer by Iterative Cell Movement Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Guxin Cui and Evangeline F.Y. Young.
Coupling-Aware Length-Ratio- Matching Routing for Capacitor Arrays in Analog Integrated Circuits Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang and Hui-Fang.
Layer Assignment Algorithm for RLC Crosstalk Minimization Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong Tsinghua University.
38 th Design Automation Conference, Las Vegas, June 19, 2001 Creating and Exploiting Flexibility in Steiner Trees Elaheh Bozorgzadeh, Ryan Kastner, Majid.
ER UCLA UCLA ICCAD: November 5, 2000 Predictable Routing Ryan Kastner, Elaheh Borzorgzadeh, and Majid Sarrafzadeh ER Group Dept. of Computer Science UCLA.
Processing Rate Optimization by Sequential System Floorplanning Jia Wang 1, Ping-Chih Wu 2, and Hai Zhou 1 1 Electrical Engineering & Computer Science.
Circuit Simulation Based Obstacle-Aware Steiner Routing Yiyu Shi, Paul Mesa, Hao Yu and Lei He EE Department, UCLA Partially supported by NSF Career Award.
Metal Layer Planning for Silicon Interposers with Consideration of Routability and Manufacturing Cost W. Liu, T. Chien and T. Wang Department of CS, NTHU,
RLC Interconnect Modeling and Design Students: Jinjun Xiong, Jun Chen Advisor: Lei He Electrical Engineering Department Design Automation Group (
CDCTree: Novel Obstacle-Avoiding Routing Tree Construction based on Current Driven Circuit Model Speaker: Lei He.
Chih-Hung Lin, Kai-Cheng Wei VLSI CAD 2008
A Topology-based ECO Routing Methodology for Mask Cost Minimization Po-Hsun Wu, Shang-Ya Bai, and Tsung-Yi Ho Department of Computer Science and Information.
Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.
Authors: Jia-Wei Fang,Chin-Hsiung Hsu,and Yao-Wen Chang DAC 2007 speaker: sheng yi An Integer Linear Programming Based Routing Algorithm for Flip-Chip.
Escape Routing For Dense Pin Clusters In Integrated Circuits Mustafa Ozdal, Design Automation Conference, 2007 Mustafa Ozdal, IEEE Trans. on CAD, 2009.
Global Routing.
1 Coupling Aware Timing Optimization and Antenna Avoidance in Layer Assignment Di Wu, Jiang Hu and Rabi Mahapatra Texas A&M University.
A Polynomial Time Approximation Scheme For Timing Constrained Minimum Cost Layer Assignment Shiyan Hu*, Zhuo Li**, Charles J. Alpert** *Dept of Electrical.
Solving Hard Instances of FPGA Routing with a Congestion-Optimal Restrained-Norm Path Search Space Keith So School of Computer Science and Engineering.
Wen-Hao Liu 1, Yih-Lang Li 1, and Kai-Yuan Chao 2 1 Department of Computer Science, National Chiao-Tung University, Hsin-Chu, Taiwan 2 Intel Architecture.
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig 1 EECS 527 Paper Presentation High-Performance.
Archer: A History-Driven Global Routing Algorithm Mustafa Ozdal Intel Corporation Martin D. F. Wong Univ. of Illinois at Urbana-Champaign Mustafa Ozdal.
An Efficient Clustering Algorithm For Low Power Clock Tree Synthesis Rupesh S. Shelar Enterprise Microprocessor Group Intel Corporation, Hillsboro, OR.
New Modeling Techniques for the Global Routing Problem Anthony Vannelli Department of Electrical and Computer Engineering University of Waterloo Waterloo,
Thermal-aware Steiner Routing for 3D Stacked ICs M. Pathak and S.K. Lim Georgia Institute of Technology ICCAD 07.
AUTOMATIC BUS PLANNER FOR DENSE PCBS Hui Kong, Tan Yan and Martin D.F. Wong Department of Electrical and Computer Engineering, University of Illinois at.
IO CONNECTION ASSIGNMENT AND RDL ROUTING FOR FLIP-CHIP DESIGNS Jin-Tai Yan, Zhi-Wei Chen 1 ASPDAC.2009.
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 6: Detailed Routing © KLMH Lienig 1 What Makes a Design Difficult to Route Charles.
ARCHER:A HISTORY-DRIVEN GLOBAL ROUTING ALGORITHM Muhammet Mustafa Ozdal, Martin D. F. Wong ICCAD ’ 07.
A Faster Approximation Scheme for Timing Driven Minimum Cost Layer Assignment Shiyan Hu*, Zhuo Li**, and Charles J. Alpert** *Dept of ECE, Michigan Technological.
1 Efficient Obstacle-Avoiding Rectilinear Steiner Tree Construction Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang National Taiwan.
1 ε -Optimal Minimum-Delay/Area Zero-Skew Clock Tree Wire-Sizing in Pseudo-Polynomial Time Jeng-Liang Tsai Tsung-Hao Chen Charlie Chung-Ping Chen (National.
Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building Yanfeng Wang, Qiang Zhou, Xianlong Hong, and Yici Cai Department of Computer Science and.
An Efficient Linear Time Triple Patterning Solver Haitong Tian Hongbo Zhang Zigang Xiao Martin D.F. Wong ASP-DAC’15.
Escape Routing of Mixed-Pattern Signals Based on Staggered-Pin- Array PCBs K. Wang, H. Wang and S. Dong Department of Computer Science & Technology, Tsinghua.
Simultaneous Analog Placement and Routing with Current Flow and Current Density Considerations H.C. Ou, H.C.C. Chien and Y.W. Chang Electronics Engineering,
LEMAR: A Novel Length Matching Routing Algorithm for Analog and Mixed Signal Circuits H. Yao, Y. Cai and Q. Gao EDA Lab, Department of CS, Tsinghua University,
1 L25 : Crosstalk-Concerned Physical Design (2) Jun Dong Cho Sungkyunkwan Univ. Dept. ECE Homepage :
High-Performance Global Routing with Fast Overflow Reduction Huang-Yu Chen, Chin-Hsiung Hsu, and Yao-Wen Chang National Taiwan University Taiwan.
A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design Jingyu Xu, Xianlong Hong, Tong Jing, Yici.
Optimal Relay Placement for Indoor Sensor Networks Cuiyao Xue †, Yanmin Zhu †, Lei Ni †, Minglu Li †, Bo Li ‡ † Shanghai Jiao Tong University ‡ HK University.
Placement and Routing Algorithms. 2 FPGA Placement & Routing.
Worst Case Crosstalk Noise for Nonswitching Victims in High-Speed Buses Jun Chen and Lei He.
VLSI Physical Design Automation
On-Chip Power Network Optimization with Decoupling Capacitors and Controlled-ESRs Wanping Zhang1,2, Ling Zhang2, Amirali Shayan2, Wenjian Yu3, Xiang Hu2,
Jason Cong, David Zhigang Pan & Prasanna V. Srinivas
Buffer Insertion with Adaptive Blockage Avoidance
2 University of California, Los Angeles
Jinghong Liang,Tong Jing, Xianlong Hong Jinjun Xiong, Lei He
Sheqin Dong, Song Chen, Xianlong Hong EDA Lab., Tsinghua Univ. Beijing
Jin-Yih Li Yih-Lang Li Computer & Information TSMC Science Department,
Performance Optimization Global Routing with RLC Crosstalk Constraints
Performance and RLC Crosstalk Driven Global Routing
Yiyu Shi*, Wei Yao*, Jinjun Xiong+ and Lei He*
Jianbo Dong, Lei Zhang, Yinhe Han, Ying Wang, and Xiaowei Li
Subset of Slides from Lei Li, HongRui Liu, Roberto Lu
EDA Lab., Tsinghua University
EE201C Chapter 3 Interconnect RLC Modeling
Donghui Zhang, Tian Xia Northeastern University
Communication Driven Remapping of Processing Element (PE) in Fault-tolerant NoC-based MPSoCs Chia-Ling Chen, Yen-Hao Chen and TingTing Hwang Department.
Chapter 3b Leakage Efficient Chip-Level Dual-Vdd Assignment with Time Slack Allocation for FPGA Power Reduction Prof. Lei He Electrical Engineering Department.
Jason Cong, David Zhigang Pan & Prasanna V. Srinivas
Department of Computer Science and Technology
Under a Concurrent and Hierarchical Scheme
Presentation transcript:

A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem Tong Jing, Ling Zhang, Jinghong Liang Jingyu Xu, Xianlong Hong Jinjun Xiong, Lei He CS&T Department EE Department Tsinghua University UCLA Beijing 100084, China Los Angeles, CA, USA Speaker: Jinghong Liang

ASP-DAC2005, Shanghai, China Outline 1. Introduction 2. Preliminaries 3. Our Work (AT-PO-GR Algorithm) 4. Experimental Results & Discussions 5. Conclusions November 27, 2018 ASP-DAC2005, Shanghai, China

Backgrounds VLSI / ULSI Coupling effects and crosstalk System-On-a-Chip (SOC) Clock frequency increases New challenge to global routing Global routing plays an important role in very/ultra large scale integrated circuits (VLSI/ULSI) physical design The progress in VLSI/ULSI enables system-on-a-chip (SOC) integration instead of system-on-a-board (SOB) integration Chip design is with greatly shrinking of geometries and giga-hertz clock frequencies All these advances enable us to get high-performance chips However, one of the great concerns is coupling effects and crosstalk Crosstalk elimination has become a challenge to global routing November 27, 2018 ASP-DAC2005, Shanghai, China

ASP-DAC2005, Shanghai, China Previous Work (1) The existing works can be divided into three categories Noise modeling [T. Sakurai, S. Kobayashi, and M. Node. ISCAS, 1991] Derived expressions for a coupling capacitance and a crosstalk voltage height [L. He and K. M. Lepak. ISPD, 2000] Declared that on-chip inductance, especially mutual inductance, should be considered for high-performance interconnect design and presented the effective coupling model, called the Keff model November 27, 2018 ASP-DAC2005, Shanghai, China

ASP-DAC2005, Shanghai, China Previous Work (2) Noise minimization [T. X. Xue, E. S. Kuh. IEEE Trans on CAD, 1997] Described a two-pass algorithm including region-based crosstalk risk estimation and crosstalk reduction [H. Zhou and D. F. Wong. IEEE Trans on CAD, 1999 ] Presented a cost function taking crosstalk into consideration, and is used during the phase of constructing the routing tree [J. J. Xiong and L. He. IEEE Trans on CAD, 2004] Proposed a three-phase algorithm based on crosstalk budgeting, simultaneous shield insertion and net ordering (SINO), and local refinement November 27, 2018 ASP-DAC2005, Shanghai, China

ASP-DAC2005, Shanghai, China Previous Work (3) Simultaneous noise minimization and performance optimization [L. Zhang, T. Jing, X. L. Hong, J. Y. Xu, J. J. Xiong, L.He. ASICON, 2003]----(PO-GR) [J. Y. Xu, X. L. Hong, T. Jing, L. Zhang, J. Gu. ASP-DAC, 2004] Both proposed performance optimization global routing algorithms considering crosstalk reduction. The former mainly focuses on coupling capacitance and uses spacing method. The latter considers coupling inductance and is based on shield insertion [L. Zhang, T. Jing, X. L. Hong, J. Y. Xu, J. J. Xiong, L.He. ISCAS, 2004]----(T-PO-GR) Presented an efficient RLC crosstalk reduction algorithm November 27, 2018 ASP-DAC2005, Shanghai, China

ASP-DAC2005, Shanghai, China Outline 1. Introduction 2. Preliminaries 3. Our Work (AT-PO-GR Algorithm) 4. Experimental Results & Discussions 5. Conclusions November 27, 2018 ASP-DAC2005, Shanghai, China

Global Routing Problem With the progress in multi-layer routing technology, routing area is a whole chip plane A net can be specified as a set of nodes in global routing graph (GRG) The problem of routing a net can be described as a rectilinear Steiner minimal tree (RSMT) problem of specified nodes in GRG. November 27, 2018 ASP-DAC2005, Shanghai, China

Global Routing Graph (GRG) 1 GRC GRG e v 2 1 v November 27, 2018 ASP-DAC2005, Shanghai, China

LSK Model for RLC Crosstalk Estimation 1 K f(i) g(j) gl Ni Nj gr Wire order Kij Fast computation of Ki,j: The total amount of inductive coupling induced on Nit: For all net segments Njt that are sensitive to Nit Different from earlier noise model Sakurai, the LSK model considers coupling inductance between adjacent and non-adjacent sensitive nets November 27, 2018 ASP-DAC2005, Shanghai, China

ASP-DAC2005, Shanghai, China Tabu Search The basic idea of this technology is simple, which records and taboos the local minimum points that have been reached so as to avoid getting stuck at these points and finds out new search ways that could lead to the global minimum point eventually. Select an initial solution xnow, and set Tabu list H = empty; While not meet the stop conditions do Generate a candidate list from the neighborhood of xnow that does not conflict with H; Select the best solution xnext from the candidate list; xnow = xnext; Update Tabu list H; End While There are 3 key factors in Tabu search: tabu object, tabu length, and aspiration rule November 27, 2018 ASP-DAC2005, Shanghai, China

ASP-DAC2005, Shanghai, China Outline 1. Introduction 2. Preliminaries 3. Our Work (AT-PO-GR Algorithm) 4. Experimental Results & Discussions 5. Conclusions November 27, 2018 ASP-DAC2005, Shanghai, China

Our Main Contributions Goal: Reduce the final routing area by means of improving the gross algorithm based on holistic optimization The main contribution of this paper is a min- area solution to performance and RLC crosstalk driven global routing problem The proposed algorithm can achieve smaller routing area and fewer shields under the same design constraints, yet use less running time November 27, 2018 ASP-DAC2005, Shanghai, China

ASP-DAC2005, Shanghai, China Problem Formulation Let Then we have Minimize Subject to: (1) (2) (3) Formula(1) is the congestion constraint, which forbids the overflow on each GRG edge Formula(2) guarantees the actual delay value from source i to sink j, T(i, j), is no more than the given timing constraint TD (i, j) Formula(3) sets the upper bound of LSK, , for each source sink pair ij. November 27, 2018 ASP-DAC2005, Shanghai, China

The Main Flow of AT-PO-GR Use Grrandom() to get an initial solution X0 It considers congestion and timing issues Use CtkEst() to budget and estimate crosstalk in X0 Iterate Grrandom(X0) to rip-up X0 so as to reduce its crosstalk, and get a good mid-solution Xtemp Use Gr(Xtemp) to reduce wire length, congestion, and delay Get a solution X1 Use CtkEli() to eliminate crosstalk in X1 by means of shield insertion and changing net orders Get the final result X2 November 27, 2018 ASP-DAC2005, Shanghai, China

Use Grrandom() to get an initial solution X0 A new cost formula of GRG edge taking crosstalk into account is used as follows , (4) where ct is the capacity of edge t, ft is the number of used tracks in edge t, δ is a small real number that validates formula (4) while ct is 0, is the actual congestion of edge t, K is a large integer used as the penalty factor, wt is the weighted cost of edge t, and nvt is the number of net segments in edge t that violate crosstalk constraint. Considering possible shield may be inserted due to these net segments, we add nvt in such that these edges tend to become more congested. Then, nets crossing such edges will have higher cost and thus it will be avoided. November 27, 2018 ASP-DAC2005, Shanghai, China

Use CtkEst() to budget and estimate crosstalk in X0 Firstly, Where is the crosstalk bound at sink pij for net Nj len is the total length from the source pio to sink pij. Secondly, having got , CtkEst() computes actual Kit with LSK model. At last, we can obtain Kslack for each source-sink pair ij. Kslack has the following definition. November 27, 2018 ASP-DAC2005, Shanghai, China

Use Gr(Xtemp) to get a solution X1 Transition from a local minimum point Gr() include 3 different strategies: stochastic optimization, deterministic optimization, and local enumeration optimization strategy. Grrandom() only uses stochastic optimization strategy. November 27, 2018 ASP-DAC2005, Shanghai, China

ASP-DAC2005, Shanghai, China Use CtkEli() to eliminate crosstalk in X1 by means of shield insertion and changing net orders Firstly, insert shields in each GRG region so that the crosstalk of most regions is within the given bound Secondly, insert shield in those regions which have possible remnant crosstalk, so that crosstalk is completely eliminated Finally, delete unnecessary shields so that the final area is minimized November 27, 2018 ASP-DAC2005, Shanghai, China

Pseudo code of AT-PO-GR November 27, 2018 ASP-DAC2005, Shanghai, China

ASP-DAC2005, Shanghai, China Outline 1. Introduction 2. Preliminaries 3. Our Work (AT-PO-GR Algorithm) 4. Experimental Results & Discussions 5. Conclusions November 27, 2018 ASP-DAC2005, Shanghai, China

Experimental Environments Platform Hardware: sun V880 fire workstation Software: gcc2.9.1, solaris5.8 Benchmark Data Circuits Number of nets GRG grids C2 745 9*11 C5 1764 16*18 C7 2356 avq 21581 65*67 Parameters Setting LSK bound at each sink is set to be 1000 Na=350, Nb=20, Nc=10, and Tabu length=3 November 27, 2018 ASP-DAC2005, Shanghai, China

In Comparison with Typical Algorithms (1) PO-GR [L. Zhang, T. Jing, X. L. Hong, 2003] is the first algorithm to study inductance coupling noise, timing performance and routability simultaneously at global routing level. It uses SA algorithm in its crosstalk elimination. (2) T-PO-GR [L. Zhang, T. Jing, X. L. Hong, 2004] runs much faster than PO-GR with the similar routing results. But the routing area and shield number in T-PO-GR are comparably larger than those in PO-GR We will compare our AT-PO-GR with the above algorithms focusing on area, running time, etc. November 27, 2018 ASP-DAC2005, Shanghai, China

The comparison of wire length, running time, and routing area between AT-PO-GR and PO-GR Circuit C2 C5 C7 avq AT-PO-GR Vionum (X0) 654 1600 1960 9885 Vionum (Xtmp) 608 1485 1902 9690 Decrease 5.66% 7.19% 2.96% 1.97% Vionum (X1) 622 1522 Wire length (X0) 477516 1415238 1588218 10154788 Wire length (X1) 450730 1266044 1530654 9906136 Running time (s) 84.33 245.55 336.94 6277.5 Area 150187 269304 337378 1206×986 PO-GR Wire length 471840 1327942 1606928 -- 2457.39 5738.45 9985.52 160190 269309 364366 The decrease of AT-PO-GR running time compared with PO-GR running time 3.43% 4.28% 3.37% The decrease of AT-PO-GR wire length compared with PO-GR wire length 4.47% 4.66% 4.75% The decrease of AT-PO-GR area compared with PO-GR area 7.73% 1.62% 4.38% November 27, 2018 ASP-DAC2005, Shanghai, China

The comparison of wire length, running time, and routing area between AT-PO-GR and T-PO-GR Circuit C2 C5 C7 avq AT-PO-GR Running time (s) 84.33 245.55 336.94 6277.5 Area 150187 269304 337378 1206×986 Shield numbers 166 484 665 4131 Wire length 450730 1266044 1530654 9906136 T-PO-GR 2457.39 5738.45 9985.52 -- 160190 269309 364366 204 527 684 471840 1327942 1606928 The decrease of AT-PO-GR running time / T-PO-GR running time 50.12% 42.25% 46.58% The decrease of AT-PO-GR wire length compared with T-PO-GR wire length 2.10% 3.25% 5.29% The decrease of AT-PO-GR area compared with T-PO-GR area 21.34% 12.74% 6.67% The decrease of AT-PO-GR shield numbers compared with T-PO-GR shield numbers 18.63% 8.16% 2.78% November 27, 2018 ASP-DAC2005, Shanghai, China

ASP-DAC2005, Shanghai, China Discussions Grrandom() can reduce crosstalk violation number(2%-7% ) The runtime of AT-PO-GR is no more than 5% of that of PO-GR AT-PO-GR can reduce wire length by more than 4% compared with PO-GR Running time of AT-PO-GR is about half of that of T-PO-GR The wire length of AT-PO-GR is shorter than that of T-PO-GR AT-PO-GR also gets improvements in area and shield number compared with T-PO-GR November 27, 2018 ASP-DAC2005, Shanghai, China

ASP-DAC2005, Shanghai, China Outline 1. Introduction 2. Preliminaries 3. Our Work (AT-PO-GR Algorithm) 4. Experimental Results & Discussions 5. Conclusions November 27, 2018 ASP-DAC2005, Shanghai, China

ASP-DAC2005, Shanghai, China Conclusions A min-area solution to performance and RLC crosstalk driven global routing problem has been presented in this paper The experimental results have shown that this algorithm is able to: (i) obtain routing solutions with less routing area compared with typical existing works (ii) preserve good routing results and greatly decrease running time compared with typical existing works November 27, 2018 ASP-DAC2005, Shanghai, China

ASP-DAC2005, Shanghai, China Future Work As our future work, we plan to find more specific methods to construct the Steiner tree set for crosstalk minimization, and better strategies for crosstalk budgeting November 27, 2018 ASP-DAC2005, Shanghai, China

ASP-DAC2005, Shanghai, China Thank you! Jinghong Liang(梁敬弘) Dept . of CST, Tsinghua Univ. Beijing 100084, P. R. China Tel.: +86-10-62785428 Fax: +86-10-62781489 E-mail: liangjh03@mails.tsinghua.edu.cn November 27, 2018 ASP-DAC2005, Shanghai, China