Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/ Semiconductor Device Modeling and Characterization – EE5342 Lecture 31 – Spring 2011 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/

Ideal 2-terminal MOS capacitor/diode conducting gate, area = LW Vgate -xox SiO2 y L silicon substrate tsub Vsub x ©rlc L31-20Apr2011

Band models (approx. scale) metal silicon dioxide p-type s/c Eo qcox ~ 0.95 eV Eo Eo qcSi= 4.05eV qfm= 4.1 eV for Al Ec qfs,p Eg,ox ~ 8 eV EFm Ec EFp EFi Ev Ev ©rlc L31-20Apr2011

Flat band condition (approx. scale) SiO2 p-Si q(fm-cox)= 3.15 eV q(cox-cSi)=3.1eV Ec,Ox qffp= 3.95eV EFm Ec Eg,ox~8eV EFi EFp Ev Ev ©rlc L31-20Apr2011

Equivalent circuit for Flat-Band Surface effect analogous to the extr Debye length = LD,extr = [eVt/(qNa)]1/2 Debye cap, C’D,extr = eSi/LD,extr Oxide cap, C’Ox = eOx/xOx Net C is the series comb C’Ox C’D,extr ©rlc L31-20Apr2011

Accumulation for Vgate< VFB -xox SiO2 EOx,x<0 holes p-type Si tsub Vsub = 0 x ©rlc L31-20Apr2011

Accumulation p-Si, Vgs < VFB Fig 10.4a* ©rlc L31-20Apr2011

Equivalent circuit for accumulation Accum depth analogous to the accum Debye length = LD,acc = [eVt/(qps)]1/2 Accum cap, C’acc = eSi/LD,acc Oxide cap, C’Ox = eOx/xOx Net C is the series comb C’Ox C’acc ©rlc L31-20Apr2011

Depletion for p-Si, Vgate> VFB -xox SiO2 EOx,x> 0 Depl Reg Acceptors p-type Si tsub Vsub = 0 x ©rlc L31-20Apr2011

Depletion for p-Si, Vgate> VFB Fig 10.4b* ©rlc L31-20Apr2011

Equivalent circuit for depletion Depl depth given by the usual formula = xdepl = [2eSi(Vbb)/(qNa)]1/2 Depl cap, C’depl = eSi/xdepl Oxide cap, C’Ox = eOx/xOx Net C is the series comb C’Ox C’depl ©rlc L31-20Apr2011

Inversion for p-Si Vgate>VTh>VFB Vgate> VFB EOx,x> 0 e- e- e- e- e- Depl Reg Acceptors Vsub = 0 ©rlc L31-20Apr2011

Inversion for p-Si Vgate>VTh>VFB Fig 10.5* ©rlc L31-20Apr2011

Approximation concept “Onset of Strong Inv” OSI = Onset of Strong Inversion occurs when ns = Na = ppo and VG = VTh Assume ns = 0 for VG < VTh Assume xdepl = xd,max for VG = VTh and it doesn’t increase for VG > VTh Cd,min = eSi/xd,max for VG > VTh Assume ns > 0 for VG > VTh ©rlc L31-20Apr2011

MOS Bands at OSI p-substr = n-channel Fig 10.9* ©rlc L31-20Apr2011

Equivalent circuit above OSI Depl depth given by the maximum depl = xd,max = [2eSi|2fp|/(qNa)]1/2 Depl cap, C’d,min = eSi/xd,max Oxide cap, C’Ox = eOx/xOx Net C is the series comb C’Ox C’d,min ©rlc L31-20Apr2011

MOS surface states** p- substr = n-channel ©rlc L31-20Apr2011

n-substr accumulation (p-channel) Fig 10.7a* ©rlc L31-20Apr2011

n-substrate depletion (p-channel) Fig 10.7b* ©rlc L31-20Apr2011

n-substrate inversion (p-channel) Fig 10.7* ©rlc L31-20Apr2011

Values for gate work function, fm ©rlc L31-20Apr2011

Values for fms with metal gate ©rlc L31-20Apr2011

Values for fms with silicon gate ©rlc L31-20Apr2011

References * Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997. **Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986 ©rlc L31-20Apr2011