8259 PROGRAMMABLE INTERRUPT CONTROLLER

Interrupts are used to handle the routines. Types: Maskable & Non Maskable For interrupts from multiple sources, hardware can use an external device called Programmable interrupt controller or Priority Interrupt controller. Main purpose of 8259 is to do the task of calling the ISR based on interrupt priority. It acts as multiplexer as it combines multiple interrupt input sources into a single interrupt request

Features of 8259 Supports 8 interrupt inputs from the peripherals and issues a single interrupt signal. Supports cascading of eight 8259ICs and multiplexes 64 interrupt sources to 1. Set priorities for the interrupts and provide different interrupt vector addresses. No clock is required

8259 Pin definition INT: O/p pin is used to interrupt the CPU INTA : 8259 receives interrupt acknowledgment from CPU. SP/EN: To make 8259 Slave / Master IR0-IR7: 8279 receive interrupt signals from 8 different sources. High, the requests are stored in IRR IRR stores all the levels that are currently being serviced.

8259 Pin definition Cascade Buffer/Comparator: 8259 can be used in cascaded mode. Used to expand the number of interrupt levels by cascading 2 or more 8259s.(8) 3 registers to program and control the operation of 8259: Interrupt Mask register (IMR) Interrupt Request register (IRR) In-Service Register (ISR)

IMR: ISR: IRR: To program the masking of external interrupt sources. Maintains the list of interrupts that are currently being serviced IRR: To store the interrupts that have been sensed by 8259

Control Words To service the interrupt requested, the interrupt controller must be initialized by writing control words in the control register. 2 types of Control words. Initialization command words (ICW1- ICW4) Operational command words (OCW2 – OCW3)