ECE-C 302 Lecture 15 Prawat Nagvajara Odometer Design Stack Design First-in First-out (FIFO) Design

--Below is a behavioral description of an --Odometer Design --Below is a behavioral description of an --odometer that counts in radix 10, e.g. it --counts from 000000 to 999999   Package odom_pack is Subtype my_integer is integer range (0 to 9); Type integer_array is array (natural range <>) of my_integer; end odom_pack; library ieee; use ieee.std_logic_1164.all, work.odom_pack; Entity odometer is Generic (N: natural := 6); --number of digits Port(ck,reset : in std_logic; Z : out integer_array(n-1 downto 0)); End odometer;

Architecture behav of odometer is Begin Process(ck) Variable carry : std_logic; Variable temp : integer_array(n-1 downto 0); If reset = ‘1’ then temp := (others => 0); Else Carry := ck; -- we increment the least -- significant digit Temp(0) on ck rising-edge For I in 0 to n-1 loop If Carry = ‘1’ then Temp(i) := (Temp(i) + 1) mod 10; If Temp(i) = 0 then Carry := ‘1’; else Carry := ‘0’; End if; End if; End loop; Z <= Temp; -- wire internal states to outputs End process; End behav;

… Temp (n-1) Temp(1) Temp(0) Ck Z(n-1) Z(1) Z(0) We wish to design a structural description architecture of the odometer by first designing the cell and then wiring the cells, using structural description, (i.e. for-generate construct), together as in the diagram above.

Entity cell is Port( C_in, reset : in std_logic; C_out : out std_logic; Y : out integer); End cell; Architecture behav of cell is Begin Process(C_in, reset) Variable temp: my_integer; If reset=‘1’ then temp := 0; Elsif reset=‘0’ and C_in=‘1’ and C_in’event then temp := (temp+1)mod 10; if temp = 0 then c_out<=1; else c_out<=0; end if; End if; Y <= temp; --wire memory to output End process; End behav;

Architecture struc of odom is Signal temp: std_logic_vector(0 to n-2); Component cell Port( C_in, reset : in std_logic; C_out : out std_logic; Y : out integer); End component; Begin G1: for I in 0 to n-1 generate G2: if I=0 generate PE:cell port map(ck,reset,temp(I),z(I)); end generate G2; G3: if I>0 and I<n-1 generate PE:cell port map(temp(I-1),reset,temp(I),z(I)); end generate G3; G4: if I=n-1 generate PE:cell port map(temp(I-1),reset,open,z(I)); end generate G4; End generate G1; End struc;

Stack or Last-in First-out (LIFO) Stack Base = 0xFFFF Location (Address) 0xFFE7 0xFFE8 0xFFE9 0xFFFA 0xFFFB 0xFFFC 0xFFFD 0xFFFE 0xFFFF Top-of-Stack Pointer

After 5 pops and a push Location (Address) 0xFFE7 0xFFE8 0xFFE9 0xFFFA 0xFFFB 0xFFFC 0xFFFD 0xFFFE 0xFFFF Top-of-Stack Pointer

FIFO Initially the FIFO is empty Location 1 2 3 4 5 6 7 0 (end around) Front Ptr Rear Ptr

After a Write Location 1 2 3 4 5 6 7 0 (end around) Front Ptr Rear Ptr

After three more Writes Location 1 2 3 4 5 6 7 0 (end around) Front Ptr Rear Ptr

After Two Reads Location 1 2 3 4 5 Front Ptr 6 7 0 (end around) 1 2 3 4 5 6 7 0 (end around) Front Ptr Rear Ptr

And Two More Reads The Queue is Empty (Front = Rear) Location 1 2 3 4 5 6 7 0 (end around) Front Ptr Rear Ptr

After Eight Writes The Queue is Full (Rear = Front) Location 1 2 3 4 5 6 7 0 (end around) Front Ptr Rear Ptr