Verilog for Digital Design Chapter 1: Introduction

Digital Systems

Digital Systems Digital systems surround us Electronic system operating on 0s and 1s Typically implemented on an Integrated Circuit (IC) – "chip" Desktop/laptop computers ("PCs") are the most popular examples Other increasingly common examples Consumer electronics: Cell phones, portable music players, cameras, video game consoles, electronic music instruments, ... Medical equipment: Hearing aids, pacemakers, life support systems, ... Automotive electronics: Engine control, brakes, ... Military equipment Networking components: Routers, switches, ... Many, many more...

Hardware Description Languages (HDLs)

Digital Systems and HDLs 100,000 10,000 1,000 100 10 1997 2000 2003 2006 2009 2012 2015 2018 Transistors per IC (millions) Digital Systems and HDLs Typical digital components per IC 1960s/1970s: 10-1,000 1980s: 1,000-100,000 1990s: Millions 2000s: Billions 1970s IC behavior documented using combination of schematics, diagrams, and natural language (e.g., English) 1980s Simulating circuits becoming more important Schematics commonplace Simulating schematic helped ensure circuit was correct before costly implementation Inputs: b; Outputs: x x=0 diagrams Off b ’ b x=1 x=1 x=1 schematics On1 On2 On3 natural language n1 n0 s0 s1 clk Combinational Logic State register b x "The system has four states. When in state Off, the system outputs 0 and stays in state Off until the input becomes 1. In that case, the system enters state On1, followed by On2, and then On3, in which the system outputs 1. The system then returns to state Off."

HDLs for Simulation Hardware description languages (HDLs) – Machine-readable textual languages for describing hardware Text language could be more efficient means of circuit entry than graphical language FSM outputs // CombLogic always @(State, B) begin case (State) S_Off: begin X <= 0; if (B == 0) StateNext <= S_Off; else StateNext <= S_On1; end S_On1: begin X <= 1; StateNext <= S_On2; S_On2: begin StateNext <= S_On3; S_On3: begin endcase FSM inputs 10 20 30 40 50 70 B_s X_s Clk_s Rst_s 60 80 90 110 100 Simulation

Verilog Verilog Other HDLs module DoorOpener(C,H,P,F); input C, H, P; output F; reg F; always @(C,H,P) begin F <= (~C) & (H | P); end endmodule Verilog Verilog Defined in 1985 at Gateway Design Automation Inc., which was then acquired by Cadence Design Systems C-like syntax Initially a proprietary language, but became open standard in early 1990s, then IEEE standard ("1364") in 1995, revised in 2002, and again in 2005. Other HDLs VHDL VHSIC Hardware Description Language / defined in 1980s / U.S. Dept. of Defense project / Ada-like syntax / IEEE standard ("1076") in 1987 VHDL & Verilog very similar in capabilities, differ mostly in syntax SystemC Defined in 2000s by several companies / C++ libraries and macro routines / IEEE standard ("1666") in 2005 Excels for system-level; cumbersome for logic level SystemVerilog System-level modeling extensions to Verilog / IEEE Standard ("1800") in 2005 ENTITY DoorOpener IS PORT (c, h, p: IN std_logic; f: OUT std_logic); END DoorOpener; ARCHITECTURE Beh OF DoorOpener IS BEGIN PROCESS(c, h, p) f <= NOT(c) AND (h OR p); END PROCESS; END Beh; #include "systemc.h" SC_MODULE(DoorOpener) { sc_in<sc_logic> c, h, p; sc_out<sc_logic> f; SC_CTOR(DoorOpener) SC_METHOD(comblogic); sensitive << c << h << p; } void comblogic() f.write((~c.read()) & (h.read() | p.read())); };

HDLs for Design and Synthesis

HDLs for Design and Synthesis HDLs became increasingly used for designing ICs using top-down design process Design: Converting a higher-level description into a lower-level one Describe circuit in HDL, simulate Physical design tools automatically convert to low-level IC design Describe behavior in HDL, simulate e.g., Describe addition as A = B + C, rather than as circuit of hundreds of logic gates Compact description, designers get function right first Design circuit Manually, or Using synthesis tools, which automatically convert HDL behavior to HDL circuit Simulate circuit, should match HDL FSM outputs 10 20 30 40 50 70 b_s x_s Clk_s Rst_s 60 80 90 110 100 FSM inputs HDL behavior Synthesis 10 20 30 40 50 70 b_s x_s Clk_s Rst_s 60 80 90 110 100 HDL circuit Physical design

HDLs for Synthesis Use of HDLs for synthesis is growing Circuits are more complex Synthesis tools are maturing But HDLs originally defined for simulation General language Many constructs not suitable for synthesis e.g., delays Behavior description may simulate, but not synthesize, or may synthesize to incorrect or inefficient circuit Not necessarily synthesis tool's fault! 10 20 30 40 50 70 b_s x_s Clk_s Rst_s 60 80 90 110 100 Simulate HDL behavior Synthesis HDL circuit

HDLs for Synthesis Consider the English language General and complex; many uses But use for cooking recipes is greatly restricted Chef understands: stir, blend, eggs, bowl, ... Chef may not understand: bludgeon, harmonic, forthright, castigate, ..., even if English grammar is correct If the meal turns out bad, don't blame the chef! Likewise, consider HDL language But use for synthesizing circuits is greatly restricted Synthesis tool understands: sensitivity lists, if statements, ... Synthesis tool may not understand: wait statements, while loops, ..., even if the HDL simulates correctly If the circuit is bad, don't blame the synthesis tool! This book emphasizes use of VHDL for design and synthesis 10 20 30 40 50 70 b_s x_s Clk_s Rst_s 60 80 90 110 100 Simulate HDL behavior Synthesis HDL circuit

Verilog for Digital Design This book introduces use of Verilog for design and synthesis In contrast to books that introduce the general language first, and then (maybe) describe synthesis subset No need to learn entire French language if your goal is just to write recipes in French Shows use of Verilog for increasingly complex digital systems Combinational logic design Sequential logic design Datapath components Register transfer level (RTL) design Emphasizes a very disciplined use of the language for specific purposes Book can be used as supplement to digital design textbook Specifically follows structure and examples of "Digital Design" by Frank Vahid, John Wiley and Sons, 2007 But can be used with other books too Can also be used as standalone introduction to Verilog