Christophe de La Taille * Gisèle Martin-Chassard * FCPPL 10 Microelectronics Selma Conforti * Christophe de La Taille * Gisèle Martin-Chassard * Ian Xiongbo** Wei Wei ** Wang Zheng ** *OMEGA-LAL Orsay ** IHEP Beijing http://omega.in2p3.fr

OMEGA-IHEP collaboration (2008) Collaboration laid out at Beijing in april 07 around a pekinese duckling Proposed to Host chinese pHD student in Orsay in 2008 Goal : design common chip for PM readout and sharing building blocks Later perform joint measurements in Beijing and Orsay 8/4/2010 C. de La Taille FCPPL meetinLyon

OMEGA-IHEP collaboration (2008) Wei Wei has stayed 6 months in Orsay (feb08-aug08) Long time needed to go through the visa procedure ! He has joined the PMm2 project (and paid by ANR) He has designed several parts of the ASIC PArISROC developped for PMm2 (high speed amplifier, Wilkinson ADC and TDC) He has made himself very well integrated in the design team He co-signs the publications and presentations of the ASIC (NNN08 Paris and TIPP09 Tsukuba) He participates to comparative measurements in IHEP 8/4/2010 C. de La Taille FCPPL meetinLyon

OMEGA-IHEP collaboration (2009) Yan Xiongbo has stayed one year in Orsay He arrived in nov 08 (paid by CAS) and left in oct 09 He has also participated to measurements of PARISROC1 in Orsay and design of the second version PARISROC2 He is also very well integrated in the team ! He has participated to the IN2P3 microelectronics school in Lalonde and presented his work He has participated to the TWEPP conference in Paris 8/4/2010 C. de La Taille FCPPL meetinLyon

OMEGA-IHEP collaboration in 2010 ASIC characterization work on-going in both labs Visit at IHEP in may around CALOR Technical reviews of chip design Cross measurements of PARISROC Possible collaboration on ATLAS pixels 8/4/2010 C. de La Taille FCPPL meetinLyon

PArISROC Photomultiplier Array Integrated in Sige Read Out Chip TWEPP09 Paris Selma Conforti Frédéric Dulucq Mowafak El Berni Christophe de La Taille Gisèle Martin-Chassard Wei Wei * http://omega.in2p3.fr * IHEP Beijing

PARiSROC description (1) Characteristics : 16 preamplifier inputs Variable gain :1  8 (3bits) (common on 16 channels) PMTs gain adjustment by a factor 4 (8 bits) (channel by channel) Input dynamic range : 0  300 pe (0  50pC) with 1% linearity 16 trigger outputs: Fast shaper (t=15ns) + low offset discriminator Threshold provided by common internal 10bit DAC (1/3 pe) “OR” of 16 triggers output 1 digitized and multiplexed charge output : Slow shaper with variable shaping time (t=50ns,100ns,200ns) Dual Track & Hold + multiplexed analog output or internal ADC 8 to 12-bit internal ADC (Wilkinson) for charge and fine time measurement Internal TDC : 24 bits counter (coarse) + fine 1 ns One serial output : 2channel number + BCID + Charge + time Dissipation : 5mW/ch I would like remind you of MAROC1 functionality blocks. MAROC1 contains/is composed of a variable gain preamplifier to adjust the PM gain per channel from 0 to 4. We have one multiplexed charge output where we can change the peaking time of slow shaper from 20ns to 200ns. Otherwise there are 64 trigger outputs which can be due to Bipolar Fast shaper or Unipolar Fast Shaper The unipolar Fast Shaper is followed by 3 discriminators to close to LUCID needs Each threshold is fixed by internal DAC 8/4/2010 C. de La Taille FCPPL meetinLyon

C. de La Taille FCPPL meetinLyon PMm2 project (2) The project proposes to segment the very large surface of photodetection in macro pixels made of 16 photomultiplier tubes connected to an autonomous front-end electronics. Replace large PMTs (20”) by groups of 16 smaller ones (12”) with central ASIC Independent channels charge and time measurement water-tight, common High Voltage Only one wire out (DATA + VCC) Target : 1pe efficiency Triggerless 1ns time resolution High granularity scalability Low cost PMm2 project 8/4/2010 C. de La Taille FCPPL meetinLyon

One channel analog part Ramp TDC, Ramp ADC and 10-bit DAC common to all channels 50 W ext PA 4-bit DAC Threshold 10-bit DAC Trigger Output Discri. x1 Ramp ADC Internal read Ramp TDC T&H FSH SSH VARIABLE DELAY Time output Charge OR ext. Hold Auto-trig Variable Cf 1pF;0.5p; 0.25p;0.125p;…. 7fF Adjustable values for each channel to adjust PM gain variation by a factor of 4 (8bits) Variable Cin 1p;2p;4p Common adjustable value Les 2 ramp sont commun à toutes les voies Adjustable and variable gain amplifier G= 1-8 Adjust = 1-4 8/4/2010 C. de La Taille FCPPL meetinLyon

C. de La Taille FCPPL meetinLyon PARISROC layout ADC ramp 16 analogue channels Digital part TDC ramp Bandgap Dual DAC Bias + supply Technology : AMS SiGe 0.35mm Size : 5mmX3.4mm Package : CQFP160 8/4/2010 C. de La Taille FCPPL meetinLyon

Internal Wilkinson ADC (II) The ADC is suited to a multichannel conversion Very good uniformity and linearity Linearity of 12 bit Wilkinson ADC Uniformity of 10 bit Wilkinson ADC 16 channels superimposed! 8/4/2010 C. de La Taille FCPPL meetinLyon

Overall behavior (10 bit ADC) Complete chain: Autotrigger + T&H + Internal ADC Linearity : 1% ; Noise 6 UADC 8/4/2010 C. de La Taille FCPPL meetinLyon

C. de La Taille FCPPL meetinLyon PARISROC2 Readout at 40MHz ADC at 8, 9 or 10 bits Bi-gain for the front-end (suppress the variable global gain) Slow shaper with slower gain and time constant (25, 50 and 100ns) TDC : use 2 capa to sample the 2 ramps New Bandgap (AMS library). 8/4/2010 27/11/2018 C. de La Taille FCPPL meetinLyon 13 13

PARISROC2 synoptic diagram Time output MUX Ramp TDC1 SCA fine time Added blocs Ramp TDC2 SCA fine time Selected good TDC Ramp ADC PA Charge output MUX SSH SSH SSH SCA low gain SCA high gain SSH .Hold Threshold 50 W ext gain Output VARIABLE DELAY PA ext. Hold OR Auto-trig Discri. FSH Adjustable gain amplifier Adjust = 1-4 Trigger Output Threshold Ramp TDC, Ramp ADC and 10-bit DAC common to all channels 10-bit DAC 10-bit DAC 10-bit DAC 8/4/2010 27/11/2018 C. de La Taille FCPPL meetinLyon 14 14

C. de La Taille FCPPL meetinLyon PArISROC layout Technology : AMS SiGe 0.35mm Size : 5mmX3.4mm Package : CQFP160 158 pads 8/4/2010 27/11/2018 C. de La Taille FCPPL meetinLyon 15 15

C. de La Taille FCPPL meetinLyon Conclusion Very fruitful collaboration on microelectronics between OMEGA-LAL Orsay and IHEP Good performance of common chip PArISROC Look forward to its application in common experiment We thank warmly Dr Wang Zheng and his group for their remarkable hospitality in China 8/4/2010 C. de La Taille FCPPL meetinLyon