Synthesizing SRAM timing and Periphery using Synopsis By: Jim Boley

Background and Motivation Most SoC designs require on chip memory Design time on the order of months SRAMs consume a majority of the area and power on a digital design To reduce this area, the bitcell array is made as dense as DRC will allow Bitcell array consumes a majority of the total area, therefore optimizing the periphery doesn’t result in significant area savings NBTI- negative bias temperature instability EM- electromigration TDDB- time depedent dielectric breakdown

Outline Motivation SRAM bitcell layout Synthesis of periphery Future work

Outline Motivation SRAM bitcell layout Synthesis of periphery Future work

SRAM Bitcell Layout BL WL BLB VDD PL PR XR XL Q QB NL NR

Step 1- Place PMOS Devices PR

Step 2- Place NMOS Pull Down devices PR NL NR

Step 3- Place NMOS Passgate Device PR XL XR NL NR

Step 4- Create Gate to Diffusion Contacts PL PR Q XL QB XR NL NR

Step 5- Create Diffusion-M1 Contacts PL PR Q XL QB XR NL NR

Step 6- Place M2 Strips BL BLB VDD PL PR XR XL Q QB NL NR

Step 6- Place M3 Strips BL WL BLB VDD PL PR XR XL Q QB NL NR VSS

Shared Contacts Minimize Area

Shared Contacts Minimize Area

Final Array- 16x16 53.84μm x 15.12μm = 814.1μm2

Outline Motivation SRAM bitcell layout Synthesis of periphery Future work

Decoder Synthesis module decoder( binary_in , // 4 bit binary input decoder_out , // 16-bit out enable // Enable for the decoder ); input [3:0] binary_in ; input enable ; output [15:0] decoder_out ; wire [15:0] decoder_out ; assign decoder_out = (enable) ? (1 << binary_in) : 16'b0 ; endmodule

Timing/Periphery Synthesis } BL Drivers } BLB Drivers <- Decoder output

Timing/Periphery Synthesis Inactive Read Write

Outline Motivation SRAM bitcell layout Synthesis of periphery Future work

Future Work Bitcell array- finish power grid, add body contacts, add pins ICC- integration of synthesized periphery with custom array (Milkyway) Simulation of final design

Questions?