Course Outline – Pittsburgh

Slides:



Advertisements
Similar presentations
Xilinx 6.3 Tutorial Integrated Software Environment (ISE) Set up basic environment Select Gates or Modules to Be simulated (Insert Program Code) Run Waveform.
Advertisements

April 30, A New Tool for Designer-Level Verification: From Concept to Reality April 30, 2014 Ziv Nevo IBM Haifa Research Lab.
Virtual Engineering Lab Faculty of Engineering – Cairo University Construction Management Applications January 11 th 2010.
CSCE 611: Conceptual Modeling Tools for CAD Course goals: –Design and verification methodologies for large-scale digital systems using industrial tools.
General information CSE 230 : Introduction to Software Engineering
VHDL Intro What does VHDL stand for? VHSIC Hardware Description Language VHSIC = Very High Speed Integrated Circuit Developed in 1982 by Govt. to standardize.
Wrap-Up Holger Schlingloff with help from Markus Roggenbach.
Bridging the Gap Between Theory and Hardware Mario D. Marino, G. Robins, K. Skadron and L. Wang {mdm9uw,robins,skadron,lw2aw}.cs.virginia.edu Department.
Reconfigurable Computing in the Undergraduate Curriculum Jason D. Bakos Dept. of Computer Science and Engineering University of South Carolina.
EE694v-Verification-Lect5-1- Lecture 5 - Verification Tools Automation improves the efficiency and reliability of the verification process Some tools,
1 Mon. Tues. Wed. Thurs. Fri. Week of Oct. 27 Independent project set-up Week of Nov. 3 Forest ecology lab – dress for weather Exam 2 no OH Week of Nov.
Guest Lecture by Ben Magstadt CprE 281: Digital Logic.
© 2005 The MathWorks, Inc. Advanced Technologies to Accelerate Mixed Signal Simulation Pieter J. Mosterman Senior Research Scientist The MathWorks, Inc.
CENTRE FOR FORMAL DESIGN AND VERIFICATION OF SOFTWARE
Guest Lecture by Ben Magstadt CprE 281: Digital Logic.
Software Engineering CS B Prof. George Heineman.
1 Welcome The Design Process Engineering Design. 2 Today’s Learning Outcomes By the completion of today's meeting, students should be able to: Prescribe.
David O’Hallaron Carnegie Mellon University Processor Architecture Overview Overview Based on original lecture notes by Randy.
Athena, a large scale programming lab support tool Anton Jansen, Ph.D. Student Software Engineering and ARCHitecture (SEARCH) University of Groningen The.
Some Course Info Jean-Michel Chabloz. Main idea This is a course on writing efficient testbenches Very lab-centric course: –You are supposed to learn.
Copyright © 2002 Qualis Design Corporation Industry and Textbook Overview Qualis Design Corporation PO Box 4444 Beaverton, Oregon USA Phone:
EL 3101 EL310 Hardware Description Languages Spring 2015 Instructor: Ilker Hamzaoglu Teaching Assistant: Ercan Kalalı Web Site:
TO THE COURSE ON DIGITAL DESIGN FOR INSTRUMENTATION TO THE COURSE ON DIGITAL DESIGN FOR INSTRUMENTATION.
EMT1111 Logic and Problem Solving Dr. José M. Reyes Álamo Lecture 1.
Teaching Functional Verification – Course Organization Design Automation Conference Sunday, June 9, 2002.
Teaching Functional Verification Design Automation Conference Sunday, June 9, 2002.
Object Oriented Programming Lecture 1: Introduction.
A Light-Weight C/C++ Based Tool for Hardware Verification Alexander Kamkin CTestBench Institute for System Programming of the Russian.
Lach1MAPLD 2005/241 Accessible Formal Verification for Safety-Critical FPGA Design John Lach, Scott Bingham, Carl Elks, Travis Lenhart Charles L. Brown.
Kazi ECE 6811 ECE 681 VLSI Design Automation Khurram Kazi* Lecture 9 Thanks to Automation press THE button outcomes the Chip !!! Reality or Myth *(lecture.
Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Topics Modeling with hardware description languages (HDLs).
Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Topics n Modeling with hardware description languages (HDLs).
ELEE 4303 Digital II Introduction to Verilog. ELEE 4303 Digital II Learning Objectives Get familiar with background of HDLs Basic concepts of Verilog.
Lab Exercise Management Steven P. Levitan, University of Pittsburgh Design Automation Conference Sunday, June 9, 2002.
CSCI-365 Computer Organization Lecture Note: Some slides and/or pictures in the following are adapted from: Computer Organization and Design, Patterson.
Lecture 1 – Overview (rSp06) ©2008 Joanne DeGroat, ECE, OSU -1- Functional Verification of Hardware Designs EE764 – Functional Verification of Hardware.
IS’ Application Development This course introduces students to the fundamental concepts and models of application development so that they can understand.
Teaching Digital Logic courses with Altera Technology
FPGA-Based System Design Copyright  2004 Prentice Hall PTR Topics n Modeling with hardware description languages (HDLs).
Introduction ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Thomson Engineering.
Teaching Functional Verification – Course Organization Design Automation Conference Sunday, June 9, 2002.
Agenda, Objectives, Approach Lecture Introduction © Ingo Arnold Advanced Software Engineering Duale Hochschule Baden-Württemberg.
CprE 281: Verilog Tutorial Ben Magstadt – Master’s Student Electrical Engineering.
ECE 448 – FPGA and ASIC Design with VHDL George Mason University ECE 448 Lab 2 Implementing Combinational Logic in VHDL.
VHDL From Ch. 5 Hardware Description Languages. History 1980’s Schematics 1990’s Hardware Description Languages –Increased due to the use of Programming.
Lecture 1 – Overview (rSp06) ©2008 Joanne DeGroat, ECE, OSU -1- Functional Verification of Hardware Designs EE764 – Functional Verification of Hardware.
Hankuk University of Foreign Studies Digital IC design (Gates modeling with VHDL & Modelsim)
BMTS Computer and Systems Pre-requisites :CT140 –Computer Skills Nature Of the Course: This course deals about the fundamentals of Computer such.
WEB 237 Week 2 Learning Team Planning, Brainstorming and Outlining Identify the competition, challenges and recommended process to create an eCommerce.
BIS 219 Week 4 Learning Team Where Did You Find that Book Check this A+ tutorial guideline at Learning-Team-Where-Did-You-Find-that-Book.
BIS 219 Week 5 Learning Team Where Did You Find that Book Check this A+ tutorial guideline at 219/BIS-219-Week-5-Learning-Team-Where-
BSA 385 Week 1 DQ 2 Why is cost-effective software engineering so important in today’s design and development of Information System solutions? Check this.
EMT 351/4 DIGITAL IC DESIGN Mrs. Siti Zarina Md Naziri
Lecture 0 Software Engineering Course Introduction
Topics Modeling with hardware description languages (HDLs).
Prepared By : “Mohammad Jawad” Saleh Nedal Jamal Hoso Presented To :
CMIS 102 Education for Service/tutorialrank.com
Topics Modeling with hardware description languages (HDLs).
Teaching Functional Verification
Course Agenda DSP Design Flow.
EECE 310 Software Engineering
Lecture 1.3 Hardware Description Languages (HDLs)
Student Feedback on Robotics in CS1 The Fleet!
Teaching Functional Verification – Course Organization
Xilinx/Model Technology Powerful FPGA Verification Solution
Implementing Combinational
Studies in Computer Programming
English Language Learners
Course A201: Introduction to Programming
User Forum 2011 Tutorial Survey
Presentation transcript:

Course Outline – Pittsburgh Week 1: What is verification? (Chapt 1 of Janick's book; industry perspective) Week 2: Hardware Functional Verification; review of Modelsim Week 3: Verification tools; Coverage metrics (Chap 2 of Janick’s book) Week 4: Behind the simulation engine – event and cycle simulation Week 5: Introduction to Specman and e language basics – Verisity Tutorial Week 6: Calc 1 Lab Week 7: Verification plan – strategies/testcases/testbenches (Chap 3; VA) Week 8: Calc 1 solution discussion + Calc 2 introduction Week 9: More e language constructs Week 10: Modeling structs;I/O blocks; data items– (VA) Week 11: Calc 2 Solutions and Calc 3 discussion Week 12: Modeling input relations/intervals/events – (VA) Week 13: Calc 3 solutions + Introduction to Formal Verification + Lab 4 Week 14: Introduction to Rulebase/ Rulebase lab Week 15: Rulebase lab

Student Feedback More quizzes/homework on “e” language More time with labs especially “lab 3” Work in groups on labs Start earlier with Specman/e Access to VA Appreciate change from VHDL testbench to Specman environment (when doing lab 1 in dual form) Appreciate change to rulebase from Specman Labs were most interesting part More time with Rulebase