ECE 3130 – Digital Electronics and Design

Slides:

Advertisements

Similar presentations

ENGIN112 L23: Finite State Machine Design Procedure October 27, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 23 Finite State Machine.

Advertisements

Lab 2: Finite State Machines CS 3410 Spring 2015.

Counters Discussion D8.3.

10/2/0810/2/2008ECE 561 -ECE Lecture 51 State Machine Implementation 10/2/20081ECE Lecture 5.

Lecture #24 Page 1 EE 367 – Logic Design Lecture #24 Agenda 1.State Machines Review Announcements 1.n/a.

State-machine structure (Mealy)

Review for Exam 2 Using MUXs to implement logic

Analysis of Clocked Sequential Circuits

A. Abhari CPS2131 Sequential Circuits Most digital systems like digital watches, digital phones, digital computers, digital traffic light controllers and.

CS 151 Digital Systems Design Lecture 21 Analyzing Sequential Circuits.

Sequential Design Part II. Output A(t+1) =D A = AX + BX B(t+1) =D B = AX Y = AX + BX.

1 Homework Reading –Tokheim, Section 5-10, 7-4 Machine Projects –Continue on MP4 Labs –Continue labs with your assigned section.

1 Homework Reading –Tokheim, Section 5-1, 5-2, 5-3, 5-7, 5-8 Machine Projects –Continue on MP4 Labs –Continue labs with your assigned section.

Give qualifications of instructors: DAP

ECE 301 – Digital Electronics

ECE 301 – Digital Electronics Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #17)

Digital Design Lecture 10 Sequential Design. State Reduction Equivalent Circuits –Identical input sequence –Identical output sequence Equivalent States.

Chapter 8 -- Analysis and Synthesis of Synchronous Sequential Circuits.

1 Lecture #12 EGR 277 – Digital Logic Synchronous Logic Circuits versus Combinational Logic Circuits A) Combinational Logic Circuits Recall that there.

ECE 3130 – Digital Electronics and Design Lab 6 State Machines Fall 2012 Allan Guan.

1 © 2014 B. Wilkinson Modification date: Dec Sequential Logic Circuits Previously, we described the basic building blocks of sequential circuits,

Fall 2004EE 3563 Digital Systems Design EE3563 Chapter 7, 8, 10 Reading Assignments  7.1, 7.2, 7.3  8.1, ,   8.5.1, 8.5.2,

DLD Lecture 26 Finite State Machine Design Procedure.

Analysis and Synthesis of Synchronous Sequential Circuits A “synchronizing” pulse/edge signal (clock) controls the operation of the memory portion of the.

1 State Reduction Goal: reduce the number of states while keeping the external input-output requirements unchanged. State reduction example: a: input 0.

1 Homework Reading –Tokheim, Section 5-1, 5-2, 5-3, 5-7, 5-8 Machine Projects –Continue on MP4 Labs –Continue labs with your assigned section.

ENG2410 Digital Design LAB #7 LAB #7 Sequential Logic Design “Sequence Recognizer” Using both Schematic Capture and VHDL.

A sequential logic circuit (a.k.a. state machine) consists of both combinational logic circuit(s) and memory devices (flip flops). The combinational circuits.

Sequential Circuit: Design BIL- 223 Logic Circuit Design Ege University Department of Computer Engineering.

State Machine Design State Machine Design Digital Electronics

CHAPTER 14 Digital Systems. Figure 14.1 RS flip-flop symbol and truth table Figure

Homework Reading Machine Projects Labs

ECE 3130 Digital Electronics and Design

Introduction to Advanced Digital Design (14 Marks)

Adapted by Dr. Adel Ammar

ECE 3130 – Digital Electronics and Design

Analysis of Clocked Sequential Circuit

SLIDES FOR CHAPTER 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS

COMP541 Sequential Logic – 2: Finite State Machines

FIGURE 5.1 Block diagram of sequential circuit

Digital Design Lecture 9

Sequential Circuits Most digital systems like digital watches, digital phones, digital computers, digital traffic light controllers and so on require.

ECE 301 – Digital Electronics

FINITE STATE MACHINES (FSMs)

CENG 241 Digital Design 1 Lecture 11

Digital Design Fundamentals

Digital Logic & Design Dr. Waseem Ikram Lecture No. 34.

CSE 140L Discussion Finite State Machines.

Recap D flip-flop based counter Flip-flop transition table

Digital Logic & Design Dr. Waseem Ikram Lecture No. 31.

Instructor: Alexander Stoytchev

ECE 3130 – Digital Electronics and Design

Analysis of Synchronous Sequential Circuits

D Flip-Flop Schematic Block Symbol Truth Table D Q Clk Q Clk D Q(t+1)

ECE 3130 – Digital Electronics and Design

State Machine Design State Machine Design Digital Electronics

Lecture No. 32 Sequential Logic.

DESIGN OF SEQUENTIAL CIRCUITS

Instructor: Alexander Stoytchev

SYEN 3330 Digital Systems Chapter 6 – Part 5 SYEN 3330 Digital Systems.

SYEN 3330 Digital Systems Chapter 6 – Part 3 SYEN 3330 Digital Systems.

Instructor: Alexander Stoytchev

FINITE STATE MACHINES.

ECE 3130 Digital Electronics and Design

CSE 140 Lecture 9 Sequential Networks

Instructor: Alexander Stoytchev

ECE 352 Digital System Fundamentals

Copyright Joanne DeGroat, ECE, OSU

COE 202: Digital Logic Design Sequential Circuits Part 3

Presentation transcript:

ECE 3130 – Digital Electronics and Design Lab 9 State Machines Fall 2016

What is a State Machine? A model of a machine that can be in one of several states (e.g. traffic lights) Different representations: State diagrams State tables State equations

Mealy and Moore State Machines Mealy machine Output values are determined by both the current state and the current inputs Moore machine Output values are determined solely by the current state

Objectives Design both Mealy and Moore machines to detect the sequence, 1010, in a bit pattern. Draw state tables. Implement the Mealy state machine using D flip-flops with clear pin.

Moore State Machine State Diagram State Table Present State Next State Output Input=0 Input=1 S1 (000) S1(000) S2(001) S2 (001) S3(010) S3 (010) S4(011) S4 (011) S5 (100) 1 State Diagram State Table

Mealy State Machine Current State Next State Output Input=0 Input=1 S2 (01) S3 (10) S4 (11) 1

Mealy Machine Implementation using DFF Inputs of combinational circuit Output of combinational circuit Present state Input Next state Flip-flop inputs (= Next State) output A B X DA DB Y 1

State Equations DA=A’BX’+ABX’+AB’X =BX’+AB’X DB=A’B’X+A’BX+AB’X+ABX =X Output=ABX’ All the equations should be simplified via using Karnaugh map.

Circuit Implementation

Symbol

Waveforms

Assignment Build and test the Mealy State Machine. Attach all screenshots into one PDF file, including schematic, symbol, test circuit schematic, waveforms.