Programmable Electrically Erasable Logic Devices (PEEL)

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Presentation transcript:

Programmable Electrically Erasable Logic Devices (PEEL) PEEL is a EEPLDs offered by International CMOS Technology. It can be electrically erasable and reprogrammable. These devices are PEEL18CV8 and PEEL22CV10. These are 20 and 24 pin PAL chips respectively. PEEL18CV8 has 9 dedicated inputs, 1 clock/input line, and 8 I/O pins. Each of these I/O pins can be configured as either input, output or bidirectional I/O.

Block Diagram of PEEL18CV8

PEEL18CV8 Macrocell

Each macrocell consists D flip flop and 2 multiplexers. PEEL18CV8 Macrocell PEEL18CV8 has 8 macrocells. Each macrocell consists D flip flop and 2 multiplexers. In each macrocell, D input of the flip flop is derived by ORing 8 product terms of the AND array. The flip flop is triggered on the positive edge of the clock signal. The synchronous preset and asynchronous clear inputs of the flip flop are derived from separate product terms. An additional product term is used to enable the output buffer of the each macrocell. In each macrocell, the control bits (A, B, C, D) of the mux can be programmed using EEPROM cells to select 1 of 12 configurations.

Configurations of Macrocell

Configurations of Macrocell

Configurations of Macrocell

Design a sequential circuit using PEEL18CV8

Design a sequential circuit using PEEL18CV8