Lecture No. 24 Sequential Logic
Digital & Logic Design Dr. Waseem Ikram Lecture No. 24
Recap Latch applications Gated S-R latch Gated D latch Switch debounce Burglar Alarm Gated S-R latch Gated D latch D latch parallel data storage
Recap Edge-triggered flip-flop Edge-detection circuit S-R flip-flop
D flip-flop Applications Data Storage (fig 1, 2) Synchronizing Asynchronous Inputs (fig 3,4,5,6) Parallel Data transfer (fig 7)
J-K flip-flop Edge triggered J-K flip-flop (fig 8) Discuss operation J-K flip-flop logic symbols (fig 9) J-K truth table (tab 1) J-K flip-flop timing diagram (fig 10)
J-K flip-flop applications Sequence Detector (fig 11) Frequency Divider (divide by 2) (fig 12) Frequency Divider (divide by 4) (fig 13) Shift Register (fig 14) Counter (fig 15)