Synchronous Sequential Circuits 5 Chapter Synchronous Sequential Circuits

Logic Circuits- Review Combinational Circuits Sequential Circuits Consists of logic gates whose outputs are determined from the current combination of inputs. Performs an operation that can be specified by a set of Boolean functions. Employ storage elements in addition to logic gates. Outputs are a function of the inputs and the state of the storage elements. Output depend on present value of input + past input.

Outline Storage Elements and Analysis Introduction to sequential circuits Types of sequential circuits Storage elements Latches Flip-flops Sequential circuit analysis State tables State diagrams

5.2 Sequential Circuits A Sequential circuit contains: Storage elements: Latches or Flip-Flops Combinational Logic: Implements a multiple-output switching function Inputs are signals from the outside. Outputs are signals to the outside. Other inputs, State or Present State, are signals from storage elements. The remaining outputs, Next State are inputs to storage elements. Outputs Inputs Combinational Logic State Next State Storage Elements

5.2 Sequential Circuits Sequential circuit Inputs Combina-tional Logic Outputs Storage Elements State Next State Sequential circuit Output function Outputs = g(Inputs, State) Next state function Next State = f(Inputs, State)

5.2 Sequential Circuits Types of Sequential Circuits Depends on the times at which: storage elements observe their inputs, and storage elements change their state Synchronous Behavior defined from knowledge of its signals at discrete instances of time. Storage elements (known as flip-flops stores one bit only) observe inputs and can change state only in relation to a timing signal (clock pulses from a clock (clk)) Asynchronous Behavior defined from knowledge of inputs at any instant of time and the order in continuous time in which inputs change If clock just regarded as another input, all circuits are synchronous!

5.3 Storage Elements :Latches Maintain a binary state (0 or 1) indefinitely as long as power is delivered to the circuit Switch states (01 or 10) when directed by an input signal. The major difference among storage elements are in the number of inputs they possess and in the manner in which the inputs affect the binary state. Most basic storage element. Used mainly to construct Flip-Flops. Asynchronous storage circuit. Types of latches: SR Latches S`R` Latches D Latches X = X

5.3 Storage Elements :Latches Basic (NOR) S – R Latch “Cross-coupling” two NOR gates gives the S – R Latch: Function diagram Graphic Symbol S (set) R (reset) Q R S Q

5.3 Storage Elements :Latches Q t+1 R S Q t+1=Q No change Reset to 0 1 Set to 1 undefined Basic (NOR) S – R Latch Qnext=(R+Q’ current)’ Q’next=(S+Qcurrent)’ Q’ t+1 Q t+1 Q R S 1 Q t+1=Q =0 ؟ Undefined undefined Function table

5.3 Storage Elements :Latches What about SR=11? Both Qnext and Q’next would become 0,which contradicts the assumption that Q and Q’ are always complemented. Another problem is what happen if we then make S=0 and R=0 together: Qnext = (0+0)’=1 Q’next =(0+0)’=1 But these new values go back into the NOR gates and we then get Q=Q’=0 again Qnext = (1+1)’=0 Q’next=(1+1)’=0 So the circuit enters an infinite loop , where Q and Q’ cycle between 0 and 1 forever.

5.3 Storage Elements :Latches Basic (NAND) Ś – Ŕ Latch “Cross-Coupling” two NAND gates gives the Ś -Ŕ Latch: Function diagram Graphic Symbol S (set) Q R Q S Q R (reset)

5.3 Storage Elements :Latches Q t+1 R S Undefined Reset to 1 1 Set to 0 Q t+1=Q No change Basic (NAND) Ś – Ŕ Latch Qnext=(S.Q’ current)’ Q’next=(R.Qcurrent)’ Q’ t+1 Q t+1 Q R S ? 1 Function table

5.3 Storage Elements :Latches Clocked S - R Latch 1 S` R` S R Q C Adding two NAND gates to the basic Ś - Ŕ NAND latch gives the clocked S – R latch: Has a time sequence behavior similar to the basic S-R latch except that the S and R inputs are only observed when the line C is high. C means “control” or “clock”.

D Latch(Transparent Latch) 5.3 Storage Elements :Latches D Latch(Transparent Latch) Adding an inverter to the S-R Latch, gives the D Latch: Note that there are no “indeterminate” states! (solves the S-R latch problem) D Latch(Transparent Latch) D Q C C D Q

5.3 Storage Elements :Latches D Latch(Transparent Latch) C D Next state of Q x No change 1 Q=0, reset state Q=1 , set state Qnext=((D.C)’.Q’ current)’ Q’next=((D’.C)’.Q current)’ Q D Q(t+1) 1 Q t+1 D 1

5.4: Sequential Circuits :Flip-Flops The latch timing problem Master-slave flip-flop Edge-triggered flip-flop Other flip-flops JK flip-flop T flip-flop

5.4: Sequential Circuits :Flip-Flops The Latch Timing Problem In a sequential circuit, paths may exist through combinational logic: From one storage element to another From a storage element back to the same storage element The combinational logic between a latch output and a latch input may be as simple as an interconnect For a clocked D-latch, the output Q depends on the input D whenever the clock input C has value 1

5.4: Sequential Circuits :Flip-Flops The Latch Timing Problem C D Q Y Clock Consider the following circuit: Suppose that initially Y = 0. As long as C = 1, the value of Y continues to change (in the level of clock pulse) The changes are based on the delay present on the loop through the connection from Y back to Y. This behavior is clearly unacceptable. Desired behavior: Y changes only once per clock pulse Clock Y

5.4: Sequential Circuits :Flip-Flops Timing A trigger: The state of a latch or flip-flop is switched by a change of the control input.

5.4: Sequential Circuits :Flip-Flops The Latch Timing Problem The key of proper operation is it to trigger it only during a signal transition (negative or positive) A solution to the latch timing problem is to break the closed path from Y to Y within the storage element The commonly-used, path-breaking solutions replace the clocked D-latch with: a master-slave flip-flop an edge-triggered flip-flop

5.4: Sequential Circuits :Flip-Flops Master Slave Master-Slave Flip-Flop Y C D Q Consists of two clocked D latches in series with the clock on the second latch inverted What happened when c=1? The data from D input is transferred to the master . The slave is disabled . Any change in the input change the master output ( Y ) but can’t effect the slave output .

5.4: Sequential Circuits :Flip-Flops Master-Slave Flip-Flop What happened when C=0? The master is disabled . The slave is enable. The value of ( Y ) is transferred to the slave as input . The output ( Q ) is equal ( Y ) . Conclusion: The output of the F-F. can change only during the transition of clock from 1 to 0 or at Trigger by the negative edge The output is the value stored in the master stage immediately before the negative edge. What about positive edges? C D Q Y Master Slave

5.4: Sequential Circuits :Flip-Flops Timing

Graphic Symbols

Graphic Symbols

Other flip-flops Other F-Fs can be built using D F-F There are four operations on a F-F - set to 1 - Reset to 0 - toggle ( complement ) of Q - nothing There are two F-F - JK F-F - T F-F

JK Flip-Flops

JK Flip-Flops D = JQ’ + K’Q Q t+1 K J No change Q t+1 = Q Reset to 0 1 Reset to 0 1 Set to 1 Complement Q t+1= Q’

T Flip-Flops T Flip-Flops

T Flip-Flops

Characteristic Table

Characteristic Table

Characteristic Equations

State Equation

State Equation

Analysis This circuit consist of : 2 D F-F A and B Input x Output Y Qt+1 = D A= D A B = D B

State Table

State Diagram

Input / output state

Analysis 1 D F-F ( A ) 2 Input X , Y Qt+1 = D D = A  X  y

Analysis 2 JK F-F (A , B) Input x Q t+1 = JQ’ + K’Q

Analysis 2 T F-F ( A, B ) 1 input X 1 output Y Qt+1 = T  Q The input equations are T_A = BX T_B = X The out put equation is Y = AB The characteristic equations are : At+1 = T_A  A = BX  A = BX(A’) + (BX)’A = A’BX + AB’ + AX’ Bt+1 = X  B

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