Amr Amin Preeti Mulage UCLA CKY Group STT-RAM Test Chip #1 Weekly Status Report Date: Wed Oct-28-2009 Amr Amin Preeti Mulage UCLA CKY Group

Top Cell Schematic Reused Blocks: Designed Blocks: Row pre-decoder Column pre-decoder Row Decoder I/O buffers Designed Blocks: Memory array COL MUX Sense amp

Memory Array Schematic 6416 storage cells 64 2 reference cells Need to add dummy cells

Memory Cell Schematic Rmtj = 400-Ohm and 800-Ohm

COL MUX Schematic

MUX Layout Estimate Pitch = 1.45μm Length = 14μm

Sense Amp Schematic

Current Sense Amp Schematic

SA Layout Estimate Area = 33μm  31μm (v.s. 26μm  18μm)

Latch Schematic

SRAM Layout Row DEC COL MUX Row PreDEC Sense Amps COL PreDEC I/O Buffers CLK GEN COL MUX Row DEC

Chip Layout Floor Plan Area estimate: Timing circuits are not included 200μm120μm Timing circuits are not included