BIC 10503: COMPUTER ARCHITECTURE Chapter 3 Memory Organization (Part 2) INTERNAL MEMORY

Semiconductor Memory Basic elements is the memory cell. Common Properties of memory cell:- They exhibit 2 stable states, to represent binary 1 and 0 They are capable of being written into, to set the state They are capable of being read, to sense the state

Semiconductor Memory RAM Misnamed as all semiconductor memory is random access Read/Write Volatile Temporary storage Static or dynamic

Random-Access Memory (RAM)

Dynamic RAM ( DRAM ) Characteristics of DRAM Bits stored as charge in capacitors Charges leak Need refreshing even when powered Simpler construction Smaller per bit Less expensive Slower Main memory Essentially analogue Level of charge determines value

DRAM Operation Address line active when bit read or written Write Read Transistor switch closed / open Write Voltage to bit line High for 1 low for 0 Then signal address line Transfers charge to capacitor Read Address line selected transistor turns on Charge from capacitor fed via bit line to sense amplifier Compares with reference value to determine 0 or 1 Capacitor charge must be restored

Static RAM ( SRAM ) Characteristics of SRAM Bits stored as on/off switches No charges to leak No refreshing needed when powered Does not need refresh circuits More complex construction Larger size per bit More expensive Faster Cache Digital Uses flip-flops

Static RAM (SRAM) Cell Transistor arrangement gives stable logic state C1 high, C2 low T1 T4 off, T2 T3 on State 0 C2 high, C1 low T2 T3 off, T1 T4 on Address line transistors T5 T6 is switch Write – apply value to B & compliment to B Read – value is on line B

SRAM vs DRAM Both volatile Dynamic cell Static Power needed to preserve data Dynamic cell Simpler to build, smaller More dense Less expensive Needs refresh Larger memory units Static Faster Cache

Read Only Memory (ROM) Permanent storage Application of ROM: Nonvolatile Application of ROM: Microprogramming Library subroutines Systems programs (BIOS) Function tables

Types of ROM Written during manufacture Programmable (once) Very expensive for small runs Programmable (once) PROM Needs special equipment to program Read “mostly” Erasable Programmable (EPROM) Erased by UV Electrically Erasable (EEPROM) Takes much longer to write than read Flash memory Modern type of EEPROM Erase whole memory electrically

Semiconductor Memory Types

Main Memory Organization Simple: CPU, Cache, Bus, Memory are same width (32 bits) CPU Cache BUS M 1-word-wide memory M CPU Cache BUS Wide Memory MUX M Bank bank bank bank 0 1 2 3 CPU Cache BUS Interleaved Memory Wide: CPU/Mux 1 word Mux/Cache, Bus, Memory N words (Alpha: 64 bits & 256 bits) Interleaved: CPU, Cache, Bus 1 word Memory N Modules (4 Modules) Each bank can independently serve memory read/write request

Error Correction A semiconductor memory is subject to errors: Hard Failure Permanent physical defect Memory cell or cells affected cannot reliably store data but become stuck at 0 or 1 or switch erratically between 0 and 1 Can be caused by: Harsh environmental abuse Manufacturing defects Wear Soft Error Random, non-destructive event that alters the contents of one or more memory cells No permanent damage to memory Power supply problems Alpha particles

Error Correcting Code Function

Error Correcting Code Function (cont) Three possible results of Compare: No errors are detected. The fetched data bits are sent out. An error is detected, and it is possible to correct the error. The data bits plus error correction bits are fed into a corrector, which produces a corrected set of M bits to be sent out. An error is detected, but it is not possible to correct it. This condition is reported.

Hamming Error Correcting Code The simplest error-correcting codes is the Hamming code use Venn diagrams to illustrate Example on 4-bit words (M = 4). Assign the 4 data bits to the inner compartments The remaining compartments are filled with what are called parity bits. Rule: Total number of 1s in a circle is even (Figure5.8b). If an error changes one of the data bits (Figure 5.8c), it is easily found. By checking the parity bits, discrepancies are found in circle A and circle C but not in circle B. Error is detected in intersection in A and C but not B. Correction to be made; change 0 to 1

Advanced DRAM Organization SDRAM One of the most critical system bottlenecks when using high-performance processors is the interface to main internal memory The traditional DRAM chip is constrained both by its internal architecture and by its interface to the processor’s memory bus A number of enhancements to the basic DRAM architecture have been explored: DDR-DRAM RDRAM

Synchronous DRAM (SDRAM) Characteristics of SDRAM :- Exchanges data with the processor synchronized to an external clock signal. Running at the full speed of the processor (no processor wait states) Burst mode allows SDRAM to set up stream of data and send it out in block May employ multiple-bank internal architecture (support on-chip parallelism)

Rambus DRAM (RDRAM) Characteristics of RDRAM :- Memory requested/transmitted over the high-speed bus Request contains the desired address, the type of operation, and the number of bytes in the operation High clock speeds Higher cost Operates at high temperature RDRAM memory with integrated heat spreader

Double Data Rate SDRAM (DDR SDRAM) Previous SDRAM can only send data once per bus clock cycle Characteristics of DDR SDRAM:- DDR SDRAM can send data twice per clock cycle Low latency Low cost (compared to RDRAM)

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