Finite State Machines Experiment 4 Introduction ECE 448 – FPGA and ASIC Design with VHDL ECE 448 – FPGA and ASIC Design with VHDL George Mason University

Sequence detector ECE 448 – FPGA and ASIC Design with VHDL

Our Example Non-resetting detector of the sequence: (10)+ (11) sc sb sa Input: 001010010111010110101010101100101 Output: 000000000010000010000000000100000 ECE 448 – FPGA and ASIC Design with VHDL

Our Example Joystick left = ‘1’ Joystick right = ‘0’ ECE 448 – FPGA and ASIC Design with VHDL

Moore State Diagram ECE 448 – FPGA and ASIC Design with VHDL

Moore Machine - ASM Chart ECE 448 – FPGA and ASIC Design with VHDL

Mealy State Diagram ECE 448 – FPGA and ASIC Design with VHDL

Mealy Machine - ASM Chart ECE 448 – FPGA and ASIC Design with VHDL

Questions? ECE 448 – FPGA and ASIC Design with VHDL