Lecture 5 Fault Modeling Why model faults? Some real defects in VLSI and PCB Common fault models Stuck-at faults Single stuck-at faults Fault equivalence Fault dominance and checkpoint theorem Classes of stuck-at faults and multiple faults Transistor faults Summary Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

Why Model Faults? I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing) Real defects (often mechanical) too numerous and often not analyzable A fault model identifies targets for testing A fault model makes analysis possible Effectiveness measurable by experiments Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

Some Real Defects in Chips Processing defects Missing contact windows Parasitic transistors Oxide breakdown . . . Material defects Bulk defects (cracks, crystal imperfections) Surface impurities (ion migration) Time-dependent failures Dielectric breakdown Electromigration Packaging failures Contact degradation Seal leaks Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation - Semiconductor Devices and Circuits, Wiley, 1981. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

Occurrence frequency (%) Observed PCB Defects Defect classes Shorts Opens Missing components Wrong components Reversed components Bent leads Analog specifications Digital logic Performance (timing) Occurrence frequency (%) 51 1 6 13 8 5 Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

Common Fault Models Single stuck-at faults Transistor open and short faults Memory faults PLA faults (stuck-at, cross-point, bridging) Functional faults (processors) Delay faults (transition, path) Analog faults For more examples, see Section 4.4 (p. 60-70) of the book. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

Fault Tolerant Digital System Desgin 5 week Fault Tolerant Digital System Desgin

Fault Tolerant Digital System Desgin x 5 week Fault Tolerant Digital System Desgin

Fault Tolerant Digital System Desgin 5 week Fault Tolerant Digital System Desgin

1 0/ 1 1 1 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

Fault Tolerant Digital System Desgin 5 week Fault Tolerant Digital System Desgin

Fault Tolerant Digital System Desgin Z(0 1) = Z(1 0) =0 AND OR Z(0 1) = Z(1 0) =1 5 week Fault Tolerant Digital System Desgin

Fault Tolerant Digital System Desgin x x ( NFBF) x x ( FBF) 5 week Fault Tolerant Digital System Desgin

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

Fault Tolerant Digital System Desgin 5 week Fault Tolerant Digital System Desgin

Fault Tolerant Digital System Desgin 1 1 5 week Fault Tolerant Digital System Desgin

Single Stuck-at Fault Three properties define a single stuck-at fault Only one line is faulty The faulty line is permanently set to 0 or 1 The fault can be at an input or output of a gate Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults Faulty circuit value Good circuit value s-a-0 c j 0(1) a d 1(0) g 1 h z i 1 b e 1 k f Test vector for h s-a-0 fault Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

001,011,100,110 Copyright 2001, Agrawal & Bushnell   001,011,100,110 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

Fault Equivalence Number of fault sites in a Boolean gate circuit = #PI + #gates + # (fanout branches). Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2. If faults f1 and f2 are equivalent then the corresponding faulty functions are identical. Fault collapsing: All single faults of a logic circuit can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

Fault Tolerant Digital System Desgin 5 week Fault Tolerant Digital System Desgin

Equivalence Rules sa0 sa0 sa0 sa1 sa0 sa1 sa1 sa1 WIRE AND OR sa0 sa1 NOT sa1 sa0 sa0 sa1 sa0 sa1 sa0 sa1 sa0 NAND NOR sa1 sa0 sa0 sa1 sa1 sa0 sa1 FANOUT Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

Fault Tolerant Digital System Desgin 5 week Fault Tolerant Digital System Desgin

Equivalence Example sa0 sa1 Faults in red removed by equivalence collapsing sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 20 Collapse ratio = ----- = 0.625 32 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

Fault Tolerant Digital System Desgin 5 week Fault Tolerant Digital System Desgin

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

Fault Tolerant Digital System Desgin β α 5 week Fault Tolerant Digital System Desgin

Fault Tolerant Digital System Desgin { 00, 01, 10} 01, 10 { 11, 01, 10} 01, 10 5 week Fault Tolerant Digital System Desgin

Dominance Example All tests of F2 F1 s-a-1 001 F2 110 010 000 s-a-1 110 010 000 101 100 s-a-1 F2 011 Only test of F1 s-a-1 s-a-1 s-a-1 s-a-0 A dominance collapsed fault set Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

Checkpoints Primary inputs and fanout branches of a combinational circuit are called checkpoints. Checkpoint theorem: A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit. Total fault sites = 16 Checkpoints ( ) = 10 Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

Classes of Stuck-at Faults Following classes of single stuck-at faults are identified by fault simulators: Potentially-detectable fault -- Test produces an unknown (X) state at primary output (PO); detection is probabilistic, usually with 50% probability. Initialization fault -- Fault prevents initialization of the faulty circuit; can be detected as a potentially-detectable fault. Hyperactive fault -- Fault induces much internal signal activity without reaching PO. Redundant fault -- No test exists for the fault. Untestable fault -- Test generator is unable to find a test. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

Example: Initialization fault Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

Multiple Stuck-at Faults A multiple stuck-at fault means that any set of lines is stuck-at some combination of (0,1) values. The total number of single and multiple stuck-at faults in a circuit with k single fault sites is 3k-1. A single fault test can fail to detect the target fault if another fault is also present, however, such masking of one fault by another is rare. Statistically, single fault tests cover a very large number of multiple faults. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

Models of fault in PLA-s and PAL-s Permanent constant faults; Short-circuits; Crosspoint Faults ; appearance of CP-s in the AND array;; disappearance of CP-s from the AND array; appearence of CP-s in the OR array; disappearance of CP-s from the OR array. Classical model of fault: constant 1 and 0 (Stuck-at-0, Stuck-at-1, s-a-0, s-a-1) s-a-0 s-a-1 X f X f Short X X f1 f1 X X f2

Example. y1 = x1 x2 x3 + x1 x2 x3 + x1 x2 y2 = x1 x2 x3 + x1 x2 x 1 x 2 x 3 1 1 1 +V y 1 y 2

Permanent constant faults in PLA/PAL-s y1 = x1 x2 x3 + x1 x2 x3 + x1 x2 y1 = x1 x2 + x1 x2 + x1 x2 X3 s-a-1fault y2 = x1 x2 x3 + x1 x2 y2 = x1 x2 + x1 x2 x 1 x 2 x 3 1 1 1 +V s-a-1 y 1 y 2

Crosspoint Faults Appearance of CP-s to in the AND array Unnecessary variable Shrinkage fault y1 = x1 x2 x3 + x1 x2 x3 + x1 x2 Unnecessary CP y1 = x1 x2 x3 + x1 x2 x3 + x1 x2 x3 y2 = x1 x2 x3 + x1 x2 y2 = x1 x2 x3 + x1 x2 x3 x 1 x 2 x 3 1 1 1 +V Carnaugh Map y 1 y 2 Faultless Faulty x2x3 x2x3 y2 y2 00 01 11 10 00 01 11 10 1 1 x1 x1 1 1 1 1 1

Disappearance of CP-s from the AND array Growth fault y1 = x1 x2 x3 + x1 x2 x3 + x1 x2 CP does not exist y1 = x1 x2 x3 + x1 x2 x3 + x1 x2 y2 = x1 x2 x3 + x1 x2 y2 = x1 x2 x3 + x1 CP does not exist x 1 x 2 x 3 1 1 1 +V Carnaugh Map y 1 y 2 Faultless Faulty x2x3 x2x3 y2 y2 00 01 11 10 00 01 11 10 x1 1 1 x1 1 1 1 1 1 1 1 1

Appearance of a new CP to the OR-array Appearance fault y1 = x1 x2 x3 + x1 x2 x3 + x1 x2 y1 = x1 x2 x3 + x1 x2 x3 + x1 x2 Unnecessary CP y2 = x1 x2 x3 + x1 x2 y2 = x1 x2 x3 + x1 x2 + x1 x2 x3 x 1 x 2 x 3 1 1 1 +V Carnaugh Map y 1 y 2 Faultless Faulty x2x3 x2x3 y2 y2 00 01 11 10 00 01 11 10 x1 1 1 x1 1 1 1 1 1 1 1

Disapperance of the CP from the OR-array Disappearance fault y1 = x1 x2 x3 + x1 x2 x3 + x1 x2 CP does not exist y1 = x1 x2 x3 + x1 x2 x3 + x1 x2 y2 = x1 x2 x3 + x1 x2 y2 = x1 x2 x3 x 1 x 2 x 3 CP does not exist 1 1 1 +V Carnaugh Map y 1 y 2 Faultless Faulty x2x3 x2x3 y2 y2 00 01 11 10 00 01 11 10 1 1 x1 x1 1 1 1 1

Transistor (Switch) Faults MOS transistor is considered an ideal switch and two types of faults are modeled: Stuck-open -- a single transistor is permanently stuck in the open state. Stuck-short -- a single transistor is permanently shorted irrespective of its gate voltage. Detection of a stuck-open fault requires two vectors. Detection of a stuck-short fault requires the measurement of quiescent current (IDDQ). Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

Stuck-Open Example VDD A B C Vector 1: test for A s-a-0 (Initialization vector) Vector 2 (test for A s-a-1) pMOS FETs VDD Two-vector s-op test can be constructed by ordering two s-at tests A 1 Stuck- open B C 1(Z) Good circuit states nMOS FETs Faulty circuit states Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

Stuck-Short Example VDD A B C Test vector for A s-a-0 pMOS FETs IDDQ path in faulty circuit A 1 Stuck- short B Good circuit state C 0 (X) nMOS FETs Faulty circuit state Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5

Truth table for fault-free circuit and all possible transistor faults VDD VSS B P1 P2 N2 N1 A Z 2-input CMOS NOR gate Any transistor can be Stuck-short Also known as stuck-on Stuck-open Also known as stuck-off # fault types: k=2 Example circuit # fault sites: n=4 # single faults =2×4=8 Open Truth table for fault-free circuit and all possible transistor faults AB 00 01 10 11 Z 1 N1 stuck-open last Z N1 stuck-short IDDQ N2 stuck-open N2 stuck-short P1 stuck-open P1 stuck-short P2 stuck-open P2 stuck-short

Truth table for fault-free circuit and all possible transistor faults VDD VSS B P1 P2 N2 N1 A Z Stuck-short faults cause conducting path from VDD to VSS Can be detect by monitoring steady-state power supply current IDDQ Stuck-open faults cause output node to store last voltage level Requires sequence of 2 vectors for detection 0010 detects N1 stuck-open 2-input CMOS NOR gate Truth table for fault-free circuit and all possible transistor faults AB 00 01 10 11 Z 1 N1 stuck-open last Z N1 stuck-short IDDQ N2 stuck-open N2 stuck-short P1 stuck-open P1 stuck-short P2 stuck-open P2 stuck-short

Transistor Faults # collapsed faults = 2×T -TS+GS -TP+GP T = number of transistors TS= number of series transistors GS= number of groups of series transistors TP= number of parallel transistors GP= number of groups of parallel transistors For example circuit, # collapsed faults = 6 T=4, TS= 2, GS= 1, TP= 2, & GP= 1 Fault collapsing typically reduces number of transistor faults by 25% to 35%

Summary Fault models are analyzable approximations of defects and are essential for a test methodology. For digital logic single stuck-at fault model offers best advantage of tools and experience. Many other faults (bridging, stuck-open and multiple stuck-at) are largely covered by stuck-at fault tests. Stuck-short and delay faults and technology-dependent faults require special tests. Memory and analog circuits need other specialized fault models and tests. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 5