ConfMVM: A Hardware-Assisted Model to Confine Malicious VMs

Slides:



Advertisements
Similar presentations
Performance Evaluation of Cache Replacement Policies for the SPEC CPU2000 Benchmark Suite Hussein Al-Zoubi.
Advertisements

1 Jacob Thomas Basu Vaidyanathan Bret Olszewski Session II April 2014 POWER8 Benchmark and Performance.
FLEXclusion: Balancing Cache Capacity and On-chip Bandwidth via Flexible Exclusion Jaewoong Sim Jaekyu Lee Moinuddin K. Qureshi Hyesoon Kim.
Helper Threads via Virtual Multithreading on an experimental Itanium 2 processor platform. Perry H Wang et. Al.
Midterm Tuesday October 23 Covers Chapters 3 through 6 - Buses, Clocks, Timing, Edge Triggering, Level Triggering - Cache Memory Systems - Internal Memory.
Adaptive Cache Compression for High-Performance Processors Alaa R. Alameldeen and David A.Wood Computer Sciences Department, University of Wisconsin- Madison.
7/2/ _23 1 Pipelining ECE-445 Computer Organization Dr. Ron Hayne Electrical and Computer Engineering.
By- Jaideep Moses, Ravi Iyer , Ramesh Illikkal and
Optimizing RAM-latency Dominated Applications
Improving the Performance of Object-Oriented Languages with Dynamic Predication of Indirect Jumps José A. Joao *‡ Onur Mutlu ‡* Hyesoon Kim § Rishi Agarwal.
NVSleep: Using Non-Volatile Memory to Enable Fast Sleep/Wakeup of Idle Cores Xiang Pan and Radu Teodorescu Computer Architecture Research Lab
NICE :Network Intrusion Detection and Countermeasure Selection in Virtual Network Systems.
Protecting Data on Smartphones and Tablets from Memory Attacks
Timing Channel Protection for a Shared Memory Controller Yao Wang, Andrew Ferraiuolo, G. Edward Suh Feb 17 th 2014.
Statistical Simulation of Superscalar Architectures using Commercial Workloads Lieven Eeckhout and Koen De Bosschere Dept. of Electronics and Information.
Thread Criticality Predictors for Dynamic Performance, Power, and Resource Management in Chip Multiprocessors Abhishek Bhattacharjee and Margaret Martonosi.
Is Out-Of-Order Out Of Date ? IA-64’s parallel architecture will improve processor performance William S. Worley Jr., HP Labs Jerry Huck, IA-64 Architecture.
Revisiting Hardware-Assisted Page Walks for Virtualized Systems
ACMSE’04, ALDepartment of Electrical and Computer Engineering - UAH Execution Characteristics of SPEC CPU2000 Benchmarks: Intel C++ vs. Microsoft VC++
VGreen: A System for Energy Efficient Manager in Virtualized Environments G. Dhiman, G Marchetti, T Rosing ISLPED 2009.
Embedded System Lab. 정범종 A_DRM: Architecture-aware Distributed Resource Management of Virtualized Clusters H. Wang et al. VEE, 2015.
Kara Zaffarano SunyIT.  Detect CPU bound and I/O bound processes  Increase process priority for CPU bound processes and lower nice value  Lower priority.
Computer Organization (1) تنظيم الحاسبات (1)
Baum, Boyett, & Garrison Comparing Intel C++ and Microsoft Visual C++ Compilers Michael Baum David Boyett Holly Garrison.
CPU/BIOS/BUS CES Industries, Inc. Lesson 8.  Brain of the computer  It is a “Logical Child, that is brain dead”  It can only run programs, and follow.
Shouqing Hao Institute of Computing Technology, Chinese Academy of Sciences Processes Scheduling on Heterogeneous Multi-core Architecture.
DISSERTATION RESEARCH PLAN Mitesh Meswani. Outline  Dissertation Research Update  Previous Approach and Results  Modified Research Plan  Identifying.
Sunpyo Hong, Hyesoon Kim
Processors with Hyper-Threading and AliRoot performance Jiří Chudoba FZÚ, Prague.
E-MOS: Efficient Energy Management Policies in Operating Systems
© 2004 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice Understanding Virtualization Overhead.
Learning A Better Compiler Predicting Unroll Factors using Supervised Classification And Integrating CPU and L2 Cache Voltage Scaling using Machine Learning.
*Pentium is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries Performance Monitoring.
Thwarting cache-based side- channel attacks Yuval Yarom The University of Adelaide and Data61.
Computer Sciences Department University of Wisconsin-Madison
X. Zhang, Y. Xiao, Y. Zhang Return-Oriented Flush-Reload Side Channels on ARM and Their Implications for Android Devices Xiaokuan Zhang, Yuan Xiao, Yinqian.
Chang Hyun Park, Taekyung Heo, and Jaehyuk Huh
4- Performance Analysis of Parallel Programs
UNIVERSITY OF HOUSTON Start
MadeCR: Correlation-based Malware Detection for Cognitive Radio
X. Zhang, Y. Xiao, Y. Zhang Return-Oriented Flush-Reload Side Channels on ARM and Their Implications for Android Devices Xiaokuan Zhang, Yuan Xiao, Yinqian.
ECE Dept., Univ. Maryland, College Park
EnGarde: Mutually Trusted Inspection of SGX Enclaves
Multiscalar Processors
Written by : Thomas Ristenpart, Eran Tromer, Hovav Shacham,
Windows Server* 2016 & Intel® Technologies
Information Security – Theory vs
Guide to Operating Systems, 5th Edition
Mengjia Yan, Yasser Shalabi, Josep Torrellas
RIC: Relaxed Inclusion Caches for Mitigating LLC Side-Channel Attacks
Bruhadeshwar Meltdown Bruhadeshwar
Hoda NaghibiJouybari Khaled N. Khasawneh and Nael Abu-Ghazaleh
Haishan Zhu, Mattan Erez
Virtualization Techniques
Diptendu Kar
University of California, Riverside
Today’s agenda Hardware architecture and runtime system
Chap. 12 Memory Organization
Hyesoon Kim Onur Mutlu Jared Stark* Yale N. Patt
Mengjia Yan† , Jiho Choi† , Dimitrios Skarlatos,
Hoda NaghibiJouybari Khaled N. Khasawneh and Nael Abu-Ghazaleh
José A. Joao* Onur Mutlu‡ Yale N. Patt*
Predicting Unroll Factors Using Supervised Classification
Virtual Memory Use main memory as a “cache” for secondary (disk) storage Managed jointly by CPU hardware and the operating system (OS) Programs share main.
What Are Performance Counters?
University of Illinois at Urbana-Champaign
MicroScope: Enabling Microarchitectural Replay Attacks
Meltdown & Spectre Attacks
Srinivas Neginhal Anantharaman Kalyanaraman CprE 585: Survey Project
2019 2학기 고급운영체제론 ZebRAM: Comprehensive and Compatible Software Protection Against Rowhammer Attacks 3 # 단국대학교 컴퓨터학과 # 남혜민 # 발표자.
Presentation transcript:

ConfMVM: A Hardware-Assisted Model to Confine Malicious VMs Zirak Allaf

Contents What is Side Channel Attack? Background Detection System Overview Methodology Rresults and Discussion Conclusion and Future works

1. What is Side Channel Attack Is the action of stealing information by exploiting h/s vulnerabilities to provide unauthorised communication between two entities in shared systems The Attack Characteristics: Such attacks do not require any privileges CPU cycles were the original key factors in both attack and countermeasures There are two main attack techniques: Flush+Reload Prime+Probe

Flush+Reload Main Memory LLC Cache 𝒑𝒓𝒐𝒄𝒆𝒔𝒔𝒐𝒓 𝒄𝒐𝒓𝒆 𝒊 𝑳 𝟐 𝑳 𝟏 Attacker 𝑝𝑎𝑔𝑒 1 𝑝𝑎𝑔𝑒 2 𝑝𝑎𝑔𝑒 3 Shared area to store AES look-up table . 𝑝𝑎𝑔𝑒 𝑛 LLC Cache 𝑠𝑒𝑡 1 𝑠𝑒𝑡 2 𝑠𝑒𝑡 3 . 𝑠𝑒𝑡 𝑛 𝒑𝒓𝒐𝒄𝒆𝒔𝒔𝒐𝒓 𝒄𝒐𝒓𝒆 𝒊 𝑳 𝟐 Attacker n=3000, threshold 𝑳 𝟏 Victm loop ( 1 to n) AESEncrypt() end loop (0= to 255, step 16) end loop 𝑠𝑒𝑡 3 21 a1 loop (add=start 𝑝 2 to end 𝑝 2 ) End loop access(add) 𝑠𝑒𝑡 3 flush(add) 𝑠𝑒𝑡 3 a1 wait() 𝑠𝑒𝑡 3 a1 if time(add)<threshold accessed by victim else not accessed accessed by victim

3. Detection System Overview

4. Methodology Standard Performance Evaluation Corporation (SPEC) It is designed to provide performance measurement which can be used to compute sensitive workloads on different computer systems. SPEC benchmark suite includes 29 applications which are written in C,C++ and Fortran There two types: SPECint 2006: 12 applications (bzip2, gcc) SPECfp 2006: 17 applications (bwaves, dealII) Hardware Performance Counters (HPCs) Events Model Specific Registers (MSR) Kernel privilege There are two types of PMC: Three fixed function registers (core cycles, reference cycles and core instructions) four programmable events (e.g. L3 misses, branch predictions)

4. Methodology (cont’d) Hardware and Software Specifications HP Proliant DL360 G7 Intel’s Xeon X5650 2.66 GHz 16 GB RAM Ubuntu 14.04 K-Nearest Neighbors (k-NN) Instance-based algorithm Hamming measurements 𝐷 𝐻 = 𝑖=0 𝑘 |𝑥−𝑦|

4. Methodology (cont’d) Data collection Processor core-based profiling Preprocessing Window size = 0.2 µp Data aggregation

5. Results The distribution of ROC curves in native system

5. Results (cont’d) The distribution of ROC curves in cloud system

6. Conclusion and Future works The detection system of side channel attacks classification Hardware Performance Counter (HPCs) host system events relevant to a Flush+Reload attack 99% and 96% respectively under SPEC CPU2006 workloads Limitation and Future Work detect techniques such as Prime+Probe due to the behaviour of the malicious loop inside the program

Spinnaker Tower End slide

Questions