Polynomial Construction for Arithmetic Circuits Alan Mishchenko Robert Brayton Department of EECS UC Berkeley

Overview Introduction Half-adder and full-adder Adder tree detection Polynomial construction Using polynomials in verification Conclusion 2

Introduction Arithmetic circuit verification is the problem of proving that a given circuit implements a known arithmetic function two circuits containing arithmetic functions are equivalent It is one of the remaining strongholds in the well-studied field of formal verification and equivalence checking Many approaches have been tried, none of them seems to work well in practice This work is motivated by the need to have a reliable practical solution The most general approach is not practical, therefore… Assumption: cut-points between adders are preserved in the circuit structure

Terminology AIG is an And-Inverter Graph simple circuit data-structure only combinational AIGs are considered here AIG variable is a node in the AIG a node can be constant 0, a primary input, a two-input AND gate AIG literal is a AIG variable with a complemented attribute Bit-blasting is a process of translation into an AIG word-level operators such as adders, multipliers, selectors, etc are bit-blasted into equivalent networks composed of AIG nodes and included in the AIG representing the design CEC stands for combinational equivalence checking CEC miter is a combinational circuit whose output is equal to 0 iff two circuits are indeed equivalent LHS and RHS are parts of the CEC miter representing two copies of the design being compared

Half Adder XOR = a * !b + !a * b = !(!a * !b + a * b) Sum Carry A, B Carry Sum 00 01 1 10 11 Sum Carry HA Sum Carry XOR = a * !b + !a * b = !(!a * !b + a * b) = !(!a * !b) * !(a * b) 3 AND2 nodes

Full Adder HA FA HA Sum Carry Sum Carry Sum Carry Sum Carry A, B, C Carry Sum 000 001 1 010 011 100 101 110 111 Sum Carry Sum Carry HA FA Sum Carry HA 7 AND2 nodes A B C

Adder Tree Adder is a full-adder or a half-adder Adder tree (AT) is one or more adders feeding into each other, without any intermediate logic gates Example 1: Ripple-carry adder (RCA) Example 2: An array of RCAs adding partial products of a multiplier Example 3: Wallace tree adding partial products of a multiplier s0 s1 s2 s3 cin FA FA FA FA cout a0 b0 a1 b1 a2 b2 a3 b3 Ripple-carry adder Wallace tree of adders

Multiplier Multiplier is composed of the following blocks Product Adder tree Final stage adder (two-argument adder) Partial product accumulator (multi-argument adder) Partial product generator Multiplicants

Adder Tree Detection In this presentation, we assume that an adder tree is detected by reverse-engineering inputs/outputs and their polarity/order are known internal cut-points between FAs/HAs are known Combinational logic Adder tree Combinational logic

Polynomial Construction Rules !a => 1 – a a & b => ab a | b => a + b - ab a ^ b => a + b - 2ab MUX(a, b, c) => ab | (1 - a)c = ab + (1-a)c - ab(1-a)c = ab + c - ac

Polynomial Construction Performed from outputs to inputs It is important for smooth construction to have correct order, polarity and signedness of the outputs Otherwise polynomial will explode It is important for smooth construction to move through cuts, which cross logic only one FA/HA at a time After constructing polynomial in each cut, it should be “clean” Each monomial has only one literal and coefficient equal to the degree of 2

Using Polynomials to Verify Against the Specification Input: Polynomial constructed for a circuit and the specification of this circuit as an arithmetic expression Output: Result of checking their equivalence Solution: Construct polynomial for the specification Compare polynomial for the circuit with that for the specification

Conclusion Presented an approach to arithmetic circuit verification Procedures are being implemented in ABC and tested on industrial designs Future work includes extending the methodology to work for the case when the cut-points between adders are not present in the AIG