Alan Mishchenko University of California, Berkeley ABC Past and Future Alan Mishchenko University of California, Berkeley

Outline Introduction Concepts and algorithms Summary Brief history Use models (research, teaching, industry) ABC’s sibling (ZZ) Concepts and algorithms Data-structures And-Inverter Graphs (AIGs) Technology-independent synthesis Technology mapping Buffering and sizing Verification No HDL frontend / no physical backend Summary

Data Structures Preference is given to light-weight, custom data-structures Memory footprint should be the same on 32-bit and 64-bit platforms For example, netlist/network is designed for speed and low memory usage in typical applications AIG (And-Inverter Graph) is used to represent logic functions Mapped/logic network is seen as an annotated AIG Integer arrays are used extensively to represent Clauses in CNF solvers Cuts in a logic network Cubes in SOPs Truth tables are used to represent small functions

AIG Definition and Examples AIG is a Boolean network composed of two-input ANDs and inverters. cdab 00 01 11 10 1 F(a,b,c,d) = ab + d(ac’+bc) b c a d 6 nodes 4 levels F(a,b,c,d) = ac’(b’d’)’ + c(a’d’)’ = ac’(b+d) + bc(a+d) cdab 00 01 11 10 1 a c b d 7 nodes 3 levels

AIGs vs. Logic Networks Structural hashing Complemented edges Makes sure AIG is always stored in a compact form Is applied during AIG construction Propagates constants Ensures each node is structurally unique Complemented edges Represents inverters as attributes on the edges Leads to fast, uniform manipulation Does not use memory for inverters Leads to efficient structural hashing Regularity Uses fixed amount of memory for each node Allocates memory for nodes in a topological order Optimized for traversal in the same topological order Small static memory footprint for many applications a b c d Without hashing a b c d With hashing

Synthesis with Choices Traditional synthesis D1 D2 D3 D4 Synthesis with choices D1 HAIG D4 D2 D3

Structural Cuts in an AIG b c p q n A cut of a node n is a set of nodes in transitive fan-in such that every path from the node to PIs is blocked by nodes in the cut. A k-feasible cut means the size of the cut must be k or less. The set {p, b, c} is a 3-feasible cut of node n. (It is also a 4-feasible cut.) k-feasible cuts are important in FPGA mapping because the logic between root n and the cut nodes {p, b, c} can be replaced by a k-LUT

Synthesis: Old and New “AIG rewriting” Delay/area costs Restructuring AND2 levels/nodes Restructuring for all 4-input cuts, try all AIG subgraphs, choose the one with the min nodes under delay constraint Results Acceptable quality Acceptable runtime Problems “Over-re-structuring” Slow for large, deep logic “AIG reshaping” Delay/area cost user-specified cost for n-input AND/XOR/MUX/MAJ Restructuring iterate “mapping” and “unmapping” several times Results Comparable quality Faster runtime Problems None so far

Mapping: Old and New “Traditional” cut-based mapping iterate over the subject graph re-compute priority cuts use structural or functional matching (ICCAD’97) For standard-cell mapping use a gain-based library map both (pos and neg) phase of each node into gates select best cuts (gates) Results Acceptable quality Reasonable runtime “Improved” cut-based mapping pre-compute priority cuts iterate over the subject graph evaluate cuts using different costs use structural or functional matching For standard-cell mapping use a gain-based library map into NPN classes of functions from the library select best cuts (NPN classes) perform phase-assignment and determine gates during buffering Results Quality not known yet Expected faster runtime

A Typical Synthesis Flow Technology-independent synthesis Technology mapping Buffering and sizing These steps are not disconnected; they overlap Synthesis talks to mapping through structural choices Mapping talks to buffering through fanout estimations Buffer and sizing can be interleaved

Verification Property checking Property checking Equivalence checking D1 Property checking p Property checking Takes design and property and makes a miter (AIG) Equivalence checking Takes two designs and makes a miter (AIG) The goal is to transform AIG until the output is proved constant 0 D2 D1 Equivalence checking

Conclusion Presented ABC in a nutshell Reviewed the main concepts and algorithms Discussed a new synthesis flow