INTERCONNECTION NETWORKS Prof. Varsha Poddar Department of CSE

Requirement of interconnection structures Connection of CPUs , IOPs to input-output devices and memory modules. Connection between components having distinct physical configurations. Several different forms of interconnects.

Few examples of interconnections Time-shared common bus Multiport memory Crossbar switch Multistage switching network Hypercube system

Time-Shared Common Bus

Time-Shared Common Bus(Contd.) Multiple number of processors connected through a common path to a memory unit. Only one processor can communicate with memory or with any other processor at a given time slot. A processor wishing to initiate a transfer, first needs to determine whether the transfer bus is free or not. Else it has to wait.

Time-Shared Common Bus(Contd.) The processor issues a command to inform the destination unit, what task is to be performed. The receiver recognizes the address in the bus and responds to the control signal from sender, after which the transfer is initiated. Problem – 1. Transfer conflicts. Solution – Bus controller that introduces priorities among the requesting units.

Problem – 2. restricted to only one transfer at a time (overall transfer rate is reduced) Solution – Local buses are introduced for internal system transfer & communication.

Multiport Memory System Employs separate bus system between each memory module and each processor.

Multiport Memory System(Contd.) Each processor bus- Is connected to each memory module. Has address, data and control lines for communication with memory module. Each memory module has 4 ports – each accommodates one processor bus.

Multiport Memory System(Contd.) Memory access conflicts resolved by assigning priorities fixed to each memory port. Priority is assigned with physical positioning of each processor , e.g. CPU1 > CPU2 > CPU3 > CPU4

Multiport Memory System(Contd.) Advantage: 1. High transfer rate as multiple path between processors & memory modules. Disadvantage: 1. Expensive memory control logic. 2. Large number of cables & connectors.

Crossbar Switch A number of cross-points that are placed at the intersection of processor bus and memory module paths.

Crossbar Switch(Contd.) Each cross-point has a switch that determines the path from a processor to a memory module. Each switch has a control logic to set up a transfer path between a processor and a memory. Examines the address placed in the bus to determine its perticular memory being addressed.

Crossbar Switch(Contd.) Resolves multiple requests for access to the same memory module – on a predetermined priority basis.

Crossbar Switch(Contd.) Working principle : Cross-point switch = multiplexer + arbitration logic Arbitration logic => priority encoder Each processor generates REQ to arbitration module, the P.E. selects the processor with highest priority. Arbitration module returns ACK signal to selected processor. Processor initiates memory operation(REQ) after receiving ACK. MUX is used to select one processor out of multiple processors, based on select combination generated by arbitration module.

Detailed version of a crossbar switch

Crossbar Switch(Contd.) Advantage: Simultaneous transfer from all memory modules as there is separate path associated with each module. Disadvantage: The hardware required to implement one switch becomes quite large & complicated.

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