Developing More Advanced Testbenches ECE 448 Lab 1b Developing More Advanced Testbenches ECE 448 – FPGA and ASIC Design with VHDL George Mason University

Agenda for today Part 1: Installation and Setup of ModelSim Part 2: Introduction to Lab 1b Developing Testbenches for Sequential Circuit Part 3: Testbenches Based on Arrays of Records Part 4: Lab Exercise 1b Part 5: Demo of Lab 1a

Installation and Setup of Tools Part 1 Installation and Setup of Tools ECE 448 – FPGA and ASIC Design with VHDL

Part 2 Introduction to Lab 1b ECE 448 – FPGA and ASIC Design with VHDL

Interface : Counter

Meaning and width of inputs and outputs

Counter 1: 8-bit binary counter An n-bit binary counter increments its value with each rising edge of the clock. After reaching 2n-1, the next value is 0. For example, a 4-bit binary counter initialized with “1100” circulates through the sequence "1100", "1101", "1110", "1111", "0000", "0001", "0010", "0011", "0100", "0101", "0110", "0111", "1000", "1001", "1010", "1011", and then repeats the same sequence.

Counter 2: 2-digit decimal counter A decimal counter encodes integers in the binary-coded decimal (BCD) format. The BCD code uses 4 bits to represent a decimal digit. For example, the BCD code for the two-digit decimal number 39 is "0011 1001". The decimal counter follows the decimal counting sequence. For example, the number following 39 is 40, which is represented as "0100 0000"

Counter 3: 8-bit Gray counter An n-bit Gray counter circulates through all 2n states and its counting sequence follows the Gray code sequence In Gray code sequence only one bit is changed between two successive code words. For example, if the counter is initialized to “0000”, its consecutive values are: “0000”, “0001”, “0011”, “0010”, “0110”, “0111”, “0101”, “0100”, “1100”, “1101”, “1111”, “1110”, “1010”, “1011”, “1001”, and “1000”.

Gray counter: State changes one-bit at a time Uses a Gray incrementor

Counter 3: 8-bit Gray counter (cont.) In general, the next state can be obtained by: a) Converting the current Gray code, x, to the corresponding binary code, y using the following algorithm: 1. The Most Significant Bit (MSB) of the binary code is always equal to the MSB of the corresponding Gray code. 2. Other bits of the output binary code can be obtained by checking gray code bit at that index. If current gray code bit is 0, then copy previous binary code bit, else copy inverse of the previous binary code bit. b) Incrementing binary code, y=y+1 c) Converting the state from binary code, y, to the corresponding Gray code x, x = y XOR (y>>1).

Counter 4: 8-bit ring counter with self-correcting logic A simple ring counter is constructed by connecting the serial-out port to the serial-in port of a shift register. For example, for a 4-bit ring counter, after the "0010" pattern is loaded, the counter passes through the states “0010”, "0001", "1000", "0100", and then repeats the same sequence. The self-correcting logic allows the initialization of the counter with the sequence containing more than a single 1. For the initial state containing more than a single 1, the next value is obtained by logically shifting the current state to the left, until the state becomes “0001”.

Tasks: For each counter type, write a separate testbench, capable of verifying the operation of the counter based on the aforementioned specifications. Each testbench, should quickly reject 3 out of 4 counters, and continue simulation for the correct counter until all possible combinations of the initial value and internal states are explored. Verify the operation of each testbench, for four different counters, using ModelSim Intel FPGA. Match each provided post-synthesis VHDL code with the corresponding counter name and specification.

Deliverables: VHDL code of the four testbenches. ModelSim waveforms and messages obtained by applying each of your testbenches to each counter (in the PDF format, a total of 16 waveforms). Short report, describing your approach and findings.

Testbenches Based on Arrays of Records Part 3 Testbenches Based on Arrays of Records ECE 448 – FPGA and ASIC Design with VHDL

Records and Arrays of Test Vectors in Testbenches ECE 448 – FPGA and ASIC Design with VHDL

Records and Arrays ECE 448 – FPGA and ASIC Design with VHDL

Records and Arrays ECE 448 – FPGA and ASIC Design with VHDL

Linear testbench ECE 448 – FPGA and ASIC Design with VHDL

Linear Testbench Testbench (entity) DUV Stimulus Generator + bcd Process entity Stimulus Generator + Response Checker bcd DUV seven_seg ECE 448 – FPGA and ASIC Design with VHDL

Linear Testbench (1) ECE 448 – FPGA and ASIC Design with VHDL

Linear Testbench (2) ECE 448 – FPGA and ASIC Design with VHDL

Linear Testbench (3) ECE 448 – FPGA and ASIC Design with VHDL

Separate stimulus generation from response checking ECE 448 – FPGA and ASIC Design with VHDL

Modular Testbench Testbench (entity) Stimulus Response Generator DUV Process 1 Process 2 Stimulus Generator Response Checker bcd seven_seg DUV Test_vector_index ECE 448 – FPGA and ASIC Design with VHDL

Modular Testbench (1) ECE 448 – FPGA and ASIC Design with VHDL

Modular Testbench (2) ECE 448 – FPGA and ASIC Design with VHDL

Modular Testbench (3) ECE 448 – FPGA and ASIC Design with VHDL

Modular Testbench (4) ECE 448 – FPGA and ASIC Design with VHDL

Variables ECE 448 – FPGA and ASIC Design with VHDL

Variables - features Can only be declared within processes and subprograms (functions & procedures) Initial value can be explicitly specified in the declaration When assigned take an assigned value immediately Variable assignments represent the desired behavior, not the structure of the circuit Can be used freely in testbenches Should be avoided, or at least used with caution in a synthesizable code

Variables - Example testing: PROCESS VARIABLE error_cnt: INTEGER := 0; BEGIN FOR i IN 0 to num_vectors-1 LOOP test_operation <= test_vector_table(i).operation; test_a <= test_vector_table(i).a; test_b <= test_vector_table(i).b; WAIT FOR 10 ns; IF test_y /= test_vector_table(i).y THEN error_cnt := error_cnt + 1; END IF; END LOOP; END PROCESS testing;

Part 4 Lab Exercise 1b ECE 448 – FPGA and ASIC Design with VHDL

Interface : Debounce_Red

Tasks: Develop VHDL code of the testbench. Verify the correctness of input waveforms for the inputs reset, clk, and input generated by your testbench. Add an instantiation of DEBOUNCE_RED, compile your testbench together with a. debounce_red_synthesis_1.vhd b. debounce_red_synthesis_2.vhd and verify the operation of each model separately. Determine the behavior of the faulty model.

Part 5 Lab 1a Demos ECE 448 – FPGA and ASIC Design with VHDL