Computer Architecture and Design Lecture 6 Bus System Computer Architecture and Design Lecture 6

Micro-operation Digital Modules are best defined by Registers Microoperation : Operations performed on the data stored in them Microoperation (-op) An elementary operation performed on data stored in register(s) Results of operations may Replace previous data, or Be transferred to another register Example: Shift, Count, Clear, Load, Add, Sub, ...

Definition of RTL Hardware Organization is Best Defined by specifying Set of registers in it & their functions Sequence of -ops performed on data stored in registers Controls governing the execution of -ops RTL (Register Transfer Language) Definition: Symbolic notation describing data xfers & -ops between registers Usefulness: -ops imply the availability of hardware logic circuits that can perform specified -ops RTL can be transformed to hardware by tools

-operations that we will learn Register Transfer Bus & Memory Transfer Arithmetic -ops Logic -ops Shift -ops Arithmetic Logic Shift Unit (ALU)

Registers Notation: Capital letters (for naming) + optional numerals Name Description Usage AR Address Register To designate memory location PC Program Counter To designate next instruction IR Instruction Register To store the instr. to execute DR Data Register To store operands / results R1 General Register To store temporary data

Register Transfer Example: R2  R1 Hardware Operation  There are at least two registers (R1 & R2) in the system  There is a connected path between R1 & R2 for data movement  R2 has “parallel load” function Operation  Transfer of the content in R1 into R2  Content of R1 does not change

Notations for RTL Symbol Letters (+ Num) Parenthesis Arrow Comma Description Denotes register Denotes part of a register Denotes information xfer Separate simultaneous -ops Examples R1, AR, PC R1(0-7), R2(L) R2  R1 R2 R1, R1 R2

Bus Bus : Set of wires, one for each bit, thru which binary data are xferred Paths must exist to xfer data among many registers Control Signal determines registers for data movement Register Register Register Register Register Register Register Register Register Register Register-to-Register Connection Common Bus-based Connection

BUS Implementation MUX Tri-state Buffer

Mux-Based BUS Sender Side Receiver Side MUX selects the sender Load signal is selected Control Unit Select R1 NR x 1 MUX R2 IR DR Common Bus Load

Tri-State Bus Buffers 3-State Gates Bus line with Tri-state buffers Output : 0, 1 & High Impedance Buffer gate is the most popular Bus line with Tri-state buffers Input A Output: Y = A if C=1 H.I. If C = 0 Cmtr C Bus line for bit 0 A0 B0 C0 D0 Select 2x4 Dec. S1 S0 1 2 3 Enable E

HW #4 Design a Mux-based bus system using behavioral coding. Let “control unit” be testbench in this HW. Initialize R1=1, R2=2, R3=3, DR=4 Execute the following using testbench. R1 -> IR R1 -> DR DR -> R1 Create a text file “register.dat” to store the final values in the four registers. Submit DUT, TB, Waveform, and “register.dat”. Control Unit Select R1 NR x 1 MUX R2 IR DR Common Bus Load

module hw3_dut(clk, ); input clk; reg [15:0] R1, R2, IR, DR; always @ (posedge clk) begin if( ) IR <= R1; else if ( ) DR <= R1; . endmodule module hw3_tb; reg ; wire ; . hw3_dut( ); endmodule