STT-MRAM Tapeouts: IBM 65nm & IBM 45nm SOI Progress Update STT-MRAM Tapeouts: IBM 65nm & IBM 45nm SOI Richard Dorrance Advisor: Prof. Dejan Marković November 5, 2010

Review of MTJs MTJ = Magnetic Tunnel Junction Consists of 3 basic layers Principles of operation Spin Injector/Polarizer: Ferromagnetic layer spin-polarize a current Spin Detector: Ferromagnetic layers tend to scatter anti-parallel currents Two resistive states: RP: Low Resistance RAP: High Resistance

STT-MRAM and How it Works STT = Spin-Torque-Transfer Use current to flip free layer between two resistive states

Integrating STT-MRAM with CMOS MTJ can integrated on top of CMOS Typically after M3 or M4 MTJ

Sense Amp for High Speed MTJ Read Designed by Fengbo Read Speed: ~300ps in 65nm ~260ps in 45nm MTJ reference easily generated (“self-biased”)

Pulse Generator A similar circuit is used to measure the Read Delay of the Sense Amp

LFSR Pseudo-Random Counter LFSR = Linear Feedback Shift Register High speed counter: can be implemented with only one XOR for certain bit lengths (i.e. 2, 3, 4, … , 18, …) For N bits, it can count up to 2N-1 4 bit example: B0 B1 B2 B3 1 2 3 4 5 6 7 8 9 10 11 12 13 14

Chip Layout (IBM 65nm) Array Sizes: 27.5F2, 35F2, 50F2 Sharing: 35F2 & 50F2 27F2 50F2 35F2 SHARE

Memory Core (IBM 65nm) 450 μm R MTJ MUX 320 μm Read/Write MUX MTJ R Decoder MUX Data SC 320 μm Read/Write Config SC RD PG MUX R MTJ

Chip Layout (IBM 45nm SOI) Array Sizes: 17F2, 25F2, 40F2 Sharing: 25F2 & 40F2 17F2 25F2 40F2

Memory Core (IBM 45nm SOI) 1 8 2 3 5 6 7 4 1) MTJ Array (MTJ pitch: 0.95µm vertical by 2.3µm horizontal) 2) MUXes 3) Read/Write Circuitry 4) Decoder 5) Configuration Scan Chain 6) Write Pulse Generator & Read Delay Circuitry 7) Data Scan Chain 8) Resistor Arrays (1) MTJ Array (5) Configuration Scan Chain (2) MUXes (6) Pulse Generation/Read Delay Measurements (3) Read/Write Circuitry (7) Data Scan Chain (4) Decoder (8) Resistor Arrays

Design Comparison YEAR 2010 2009 [1] 2009 [2] 2010 [3] 2010 [4] DESIGNER UCLA Qualcomm NEC Fujitsu & UT Toshiba POWER SUPPLY [V] 1.1/1.4 1.2/1.6 1.1/1.8 1/1.5 1.2/3.3 1.2 CELL STRUCTURE 1T-1MTJ Reversed 2T-1MTJ Boosted WL Parallel MEMORY SIZE 32 kb 16 kb 32 Mb 64 Mb PROCESS [nm] 45 65 90 130 CELL SIZE [μm2] 0.1534 (17F2) to 0.3610 (40F2) 0.2750 (27.5F2) 0.5000 (50F2) 0.1026 (11F2) 1.37 (70F2) 5.53 (140F2) 0.3584 (36F2) READ TIME [ns] 0.3-1ns* <100 60 8 11 WRITE TIME 3-5ns* 10ns-1ms  91ns 9-10ns 30ns * Based on simulation results

References C.J. Lin, et al., "45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell," Electron Devices Meeting (IEDM), 2009 IEEE International , vol., no., pp.1-4, 7-9 Dec. 2009 R. Nebashi, et al., "A 90nm 12ns 32Mb 2T1MTJ MRAM," Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International , vol., no., pp.462-463,463a, 8-12 Feb. 2009 D. Halupka, et al., "Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International , vol., no., pp.256-257, 7-11 Feb. 2010 K. Tsuchida, et al., "A 64Mb MRAM with clamped-reference and adequate-reference schemes," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International , vol., no., pp.258-259, 7-11 Feb. 2010