Levels in computer design Circuit design (transistors, resistors, etc) Result is in terms of gates, flip-flops etc. Logical design Put gates and f-f’s together to build larger blocks (registers,adders, multiplexers etc.) Register Transfer Design of the datapath by linking together building blocks under the control of the control unit Processor chip description Includes datapath, control unit, on-chip caches, TLB’s etc. System description 11/30/2018 CSE471 Verilog intro

HDL’s (Hardware Description Languages) Motivation: Chip densities increase hence design complexity increases Schematics become insufficient HLL’s and, for us, HDL’s allow to express Functionality (behavior of a design) Structure (description in terms of basic components and their interconnections) Data flow HDL’s part of larger system allowing Simulation (debugging of the design; discrete event simulator) Synthesis (not in this course) 11/30/2018 CSE471 Verilog intro

Verilog Includes capabilities to describe a design’s Syntax Behavioral nature (use procedural constructs) Structural composition (use of built-in gate and user-defined primitives) Data flow nature (using “continuous assignments”) Mixed (i.e. combination of the above) Syntax C-like Has capabilities to access the internals of a design during simulation 11/30/2018 CSE471 Verilog intro

Verilog capabilities (overview) Hierarchical design using instantation of modules A module, like a procedure in a C-like language, has a name, input/output ports, and a body A module is not called like a procedure. It is instantiated. Inputs are monitored. Upon change, the output is changed. Can be done continuously, or under some conditions Output can be instantaneous, or after some delay The module stays around for the lifetime of the program 11/30/2018 CSE471 Verilog intro

Module - Behaviorial //behaviorial module AND2 (in1,in2,out); Name Port list //behaviorial module AND2 (in1,in2,out); input in1, in2; output out; wire in1,in2; reg out; always @ (in1 or in2) out = in1 & in2; endmodule Required key word “infinite-loop-like” assignment; output, necessarily a register, changes every time input changes; Wire: connection between structural elements Reg: Data Storage element 11/30/2018 CSE471 Verilog intro

Module -- Data Flow //data flow module AND2 (in1,in2,out); input in1, in2; output out; wire in1,in2, out; assign out = in1 & in2; endmodule Continuous assignment. input continuously monitored; Can be used for combinational circuits (note that “out” is a wire not a register) 11/30/2018 CSE471 Verilog intro

Module -- Structural //structural module AND2 (in1,in2,out); input in1, in2; output out; wire in1,in2, out; and u1 (out,in1,in2); endmodule Primitive logic gate 11/30/2018 CSE471 Verilog intro

Testing a module with $monitor //test for behaviorial AND2 module module tester; reg in1,in2; wire out; AND2 a2(in1,in2,out); //instantiate AND2 module initial begin //Generate test data in1 = 0; in2 = 0; #1 in2 = 1; #1 in2 = 0; in1 =1; #1 in2 = 1; #1 $finish; end initial begin // header $monitor("Time=%0d in1=%b in2=%b out=%b",$time, in1, in2, out); endmodule Need to use registers here for stable monitoring initial and always used to model sequential logic Constantly monitors input. Will display info at change in one of the variables 11/30/2018 CSE471 Verilog intro

calvin% verilog tand2beh.v and2beh.v VERILOG-XL 2.5 Dec28, 1999 10:14:28 Copyright (c) 1995 Cadence Design Systems, Inc. All Rights Reserved. Unpublished -- rights reserved under the copyright laws of the United States. …………………….. Compiling source file "tand2beh.v" Compiling source file "and2beh.v" Highest level modules: tester Time=0 in1=0 in2=0 out=0 Time=1 in1=0 in2=1 out=0 Time=2 in1=1 in2=0 out=0 Time=3 in1=1 in2=1 out=1 L11 "tand2beh.v”: $finish at simulation time 4 Names of the files with modules “tester” and “and2” 11/30/2018 CSE471 Verilog intro

Testing a module with $strobe //test for data flow AND2 module module tester; reg in1,in2; wire out; AND2 a2(in1,in2,out); //instantiate AND2 module initial begin //Generate test data #1 in1 = 0; in2 = 0; $strobe("in1=%b in2=%b out=%b",in1, in2, out); #1 in2 = 1; #1 in2 = 0; in1 =1; # 1 in2 = 1; #1 $finish; end endmodule Displays data at the end of time step 11/30/2018 CSE471 Verilog intro

calvin% verilog tand2dat.v and2dat.v VERILOG-XL 2.5 Dec 28, 1999 10:36:54 Compiling source file "tand2dat.v" Compiling source file ”and2dat.v" Highest level modules: tester Time=0 in1=0 in2=0 out=0 Time=1 in1=0 in2=1 out=0 Time=2 in1=1 in2=0 out=0 Time=3 in1=1 in2=1 out=1 L15 "tand2dat.v": $finish at simulation time 5 11/30/2018 CSE471 Verilog intro

Module Hierarchy (Basic idea) Connect modules together to form larger modules Example: Build an AND gate by 2 NAND gates in series Use same tester program as before 11/30/2018 CSE471 Verilog intro

//data flow NAND module module NAND2 (in1, in2, out); input in1, in2; output out; assign out = ~(in1 & in2); endmodule By default not specifying the type of a variable means it’s a “wire” // AND made up of 2 consecutive NAND's module AND2(in1,in2,out); input in1,in2; output out; wire w1; // to connect the 2 NAND's NAND2 nand1(in1,in2,w1); NAND2 nand2(w1,w1,out); endmodule 11/30/2018 CSE471 Verilog intro

calvin% verilog tand2beh.v nand.v and2beh.v VERILOG-XL 2.5 Dec 28, 1999 10:49:18 Compiling source file "tand2beh.v" Compiling source file "nand.v" Compiling source file "and2beh.v" Highest level modules: tester Time=0 in1=0 in2=0 out=0 Time=1 in1=0 in2=1 out=0 Time=2 in1=1 in2=0 out=0 Time=3 in1=1 in2=1 out=1 L11 "tand2beh.v": $finish at simulation time 4 11/30/2018 CSE471 Verilog intro