ECE 353 Introduction to Microprocessor Systems Week 2 Michael J. Schulte
Topics Simple P Organization Simple P Architecture Fetch-Decode-Execute model Instruction encoding Notation – bit and byte numbering 80C188EB Organization 80C188EB Subsystems
Simple P Organization A less simple architecture
A Simple P Architecture Register Transfer Expressions Simple P Operation Fetch-Decode-Execute Instruction Set Typical Operations Operand Ordering Instruction Encoding and Decoding Example Register View (or programmers’ model) of a simple P
Notation Byte Ordering for Little Endian vs. Big Endian Big Endian Most Significant Byte (MSB) Least Significant Byte (LSB) Example: int x = 0x1234; Big-endian 12 34 Motorola, SPARC (big end in first byte) Little-endian 34 12 Intel (little end in first byte) The MIPS processor and compilers support both the Big Endian and Little Endian byte-ordering conventions. The names Big Endian and Little Endian are used because of the apt analogy to the bloody feud in the classic children's book Gulliver's Travels (quod vide). The feud was between the two mythical islands, Lilliput and Blefescu, over the correct end (big or little) at which to crack an egg. In our case, the issue has to do with the "end" (most significant or least significant) of a multiple-byte data type. With Big Endian ordering, the address of a multiple-byte data type is of its most significant byte (its "big end"), whereas with Little Endian ordering, the address is of its least significant byte (its "little end"). This is shown in Figure A.14. For structures declared in a high-level language, the order of bytes in memory will differ depending on the byte ordering and the particular data type, as shown for a C structure in Figure A.15. Most UNIXes (for example, all System V) and the Internet are Big Endian. Motorola 680x0 microprocessors (and therefore Macintoshes), Hewlett-Packard PA-RISC, and Sun SuperSPARC processors are Big Endian. The Silicon Graphics MIPS and IBM/Motorola PowerPC processors are both Little and Big Endian (bi-endian). Memory Address 000 001 002 003 Big Endian Byte 3 Byte 2 Byte 1 Byte 0 MSB in the lowest memory address Little Endian MSB in the highest memory address
80C188EB Organization System Diagram 80C188EB Block Diagram A Minimal 80C188EB CPU Subsystem Memory Subsystem 220 Addressable Locations (Bytes) Memory map Unpopulated areas Physical address
80C188EB I/O Subsystems I/O Space vs. Memory Space I/O Subsystem Isolated I/O space Memory-mapped I/O on 80C188EB I/O Subsystem I/O Map PCB (Peripheral Control Block) Configuration of integrated peripherals Relocatable Integrated I/O Unit Port 1 Port 2
80C188EB Modular Core CPU CPU Efficiency BIU EU Fetch/Execute Overlap Fetch-Decode-Execute Inefficiencies BIU Interface to memory and external I/O EU Processing functions Fetch/Execute Overlap Effects of Decoupling Performance Issues What next?
Wrapping Up Homework #1 due Friday 2/4 Week 3 reading is chapters 3.5-3.9, 4, 5 from textbook
Exercise A 32-bit word with value 354298h is stored in memory at address 8744h in a little-endian system. Show the address and contents of each byte of memory used. What type of operation is described by (PC) (PC) - 43? A 20-bit address space has a 32KB RAM at base address 38000h, and a 128KB ROM at B0000h. Draw and label the memory map.
In-Class Exercise Design decode logic for the following devices with the indicated control inputs: 2Kx8 ROM (/CS, /OE) at 04XXXh 64Kx8 RAM (/CS, /OE, /WE) at A0000h Input Port (/OE) at 0378h Output Port (/WR) at 1XXXh Assume an 80C188EB address (A19:0) and control bus (/RD, /WR, /S2)
Intel SA-1110 StrongARM
80C188EB Block Diagram
RELREG
PCB
Register View of a Simple P aka “Von Neumann” or “Princeton” architecture
Register View of a Simple P with Isolated I/O space Most microprocessors do NOT have isolated I/O. The Intel x86 microprocessors do.
Register View of a Simple P with Separate Code and Data Memories aka “Harvard” architecture
80C188EB System Diagram
Minimal 80C188EB CPU Subsystem
80C188EB I/O Map
CPU and Bus Interface Unit