A Large Swing, 40-Gb/s SiGe BiCMOS Driver with Adjustable Pre-Emphasis for Data Transmission over 75W Coaxial Cable Ricardo A. Aroca & Sorin P. Voinigescu Edward S. Rogers, Sr. Dept. of Electrical & Comp. Eng., University of Toronto, Toronto, ON M5S 3G4, Canada

Outline Motivation Driver Specifications Driver Architecture and Design Measurements Transmission Experiment Conclusions

Motivation Transport 40-Gb/s over existing coaxial cable infrastructure Transceiver IC must be low-cost, highly integrated, and capable of equalizing up to 50dB of channel losses Belden 1694A TX/RX IC

Transceiver Architecture Line driver Focus on the TX, RX in development TX requires amplitude control and pre-emphasis control Place as much equalization into the TX to ease the RX specs Transmit serializer and 40-G PLL Line driver FFE DFE 40-GHz clock 40 Gb/s @ 5V 40 Gb/s @ 1 – 1.8V Timing Recovery 40-GHz clock

40-Gb/s, 75W Driver Specifications Parameter Specification Input DC level 1 - 1.8V Min Input Amplitude 200mVpp Output Swing: driving 75W driving 50W 1 – 5Vpp per side 0.8 – 4Vpp per side Gain: > 28dB > 26dB Bandwidth: > 20GHz > 25GHz S11, S22 < -10dB up to 40GHz Duty Cycle 30 - 70% Pre-Emphasis 0 - 400% PDC ~3W CMOS

Production Technology Jazz HX 0.2mm SiGe BiCMOS 0.18mm n-MOSFET fMAX = 75GHz fT = 50GHz JpkfT = 0.3mA/mm NMOS HV-HBT HV-HBT, BVceo=3.5V fMAX = 100GHz fT = 75GHz JpkfT = 2.5mA/mm2

Distributed Architecture Design 8V 75W OUTP OUTN 1 2 3 4 5 6 7 5V 75W Microstrip T-Line Sections Pre-Driver INP INN DCC AMP Amp & Pre-Emphasis Itail CNTRL IOUT = 5Vpp/(75W//75W) = 133mA  19mA/section Must fully switch the DA  predriver: 1.5Vpp, 40mA Gain of predriver = 1.5/0.2 = 18dB, 3dB/stage  6 stages Distributed pre-emphasis is implemented for the first time Amplitude control is implemented in both the DA and predriver

DA Section Schematic C R IMAIN IPRE IOFF VPRE HV-HBT fT=75GHz T-line section T-line compensation HV-HBT fT=75GHz fMAX=100GHz RC-HPF & Digital HBT fT=160GHz, fMAX=160GHz 0.18mm n-MOSFETs fT=50GHz, fMAX=75GHz

DA Section Schematic C IT R IT=IMAIN+IPRE IOFF IMAIN VPRE IPRE T-line section T-line compensation IT=IMAIN+IPRE IT IT is variable, for amplitude control at different pre-emphasis settings IOFF adjusts to ensure current through HV-HBT is constant

Driver Microphotograph 1.2mm Predriver Distributed Amplifier 2.5mm

S-parameter Measurements vs. Simulations: 10dB of Amplitude Control 22GHz 10dB

S-Parameter Measurements vs. Simulations: 25dB of Pre-Emphasis Control

40-Gb/s Eyes @ 25oC and 125oC 25oC 125oC 3Vpp 1Vpp 25oC Input: 200mVpp, 4x(231-1 PRBS) 2ps RMS jitter (1khits) ~11ps rise/fall times 1.9Vpp 125oC

40-Gb/s Pre-Emphasis @ 25oC and 125oC Input: 200mVpp, 4x(231-1 PRBS) 200-400% pre-emphasis 1Vpp 2Vpp 25oC 125oC 1.3Vpp

Maximum Output Amplitude @ 38Gb/s 3.6Vpp per side in a 50W load, 10.5ps rise time, 2.2ps RMS jitter (1.17khits)

40-Gb/s Driver Performance in 50W Parameter Target Measured Input DC level 1 - 1.8V Min Input Amplitude 200mVpp Output Swing: driving 75W driving 50W* 1 – 5Vpp per side 0.8 – 4Vpp per side 0.8 - 3.6Vpp per side Gain: driving 75W > 28dB > 26dB 36dB Bandwidth > 20GHz > 25GHz 22GHz S11, S22 (up to 40GHz) < -10dB Duty Cycle 30 - 70% 35 – 65% Pre-Emphasis 0 - 400% PDC ~3W 3.6W

40-Gb/s, 50W Driver Comparison Parameter GaAs [1] InP [3] SiGe [2] This Work fT / fMAX (GHz) 100 / 200 150 / 200 120 / 160 MOS: 50 / 75 HV-HBT: 75 / 100 Topology LD* LD Swing (per side) 1.7 - 3 1 - 5.65 3.4 0.8 - 3.6 Gain (dB) 16 30 - 36 Bandwidth (GHz) 45 22 Duty Cycle (%) 30 – 70 35 – 65 PDC (W) 2.8 3 < 3 3.6 Pre-Emphasis no 0 - 400% *LD – Lumped predriver followed by a distributed amplifier *[ ] – Reference numbers refer to those cited in the paper

Transmission Experiment over 10m, 30m and 40m of Belden Coaxial Cable INPUT TO CHANNEL BIAS 4x231-1 PRBS K-SMA-BNC RSH Source T RSH T BIAS 10m,30m,40m coax To Remote Sampling Head (RSH) AFTER CHANNEL

Equalized Channel Response INPUT TO CHANNEL AFTER CHANNEL Range of all possible equalized channel responses

10-Gb/s over 40m Coax -24dB 50mVpp No Pre-emphasis With Pre-emphasis

40- & 38-Gb/s over 10m Coax No Pre-emphasis -23dB 200mVpp 200mVpp Pre-emphasis @40Gb/s Pre-emphasis @38Gb/s

Conclusions Large swing, fully-differential 40-Gb/s SiGe BiCMOS cable driver with adjustable pre-emphasis has been presented. Key features include: Distributed pre-emphasis technique MOS-HV-HBT cascode topology Transmission experiments over Belden 1694A coax: equalization of -24dB of loss at 5GHz equalization of -22dB at 19GHz Experimental results indicate that this driver could also be used as a 50W EAM driver operating at 40 Gb/s.

Acknowledgements Jazz Semiconductor and Marco Racanelli for fabrication Gennum Corporation and NSERC for funding Jaro Pristupa for CAD support

Backup Slides

Transmission Experiment over 10m, 30m and 40m of Belden Coaxial Cable RSH RSH Source DUT To Remote Sampling Head (RSH)

38- & 30-Gb/s over 10m Coax Cable -17.7dB 30-Gb/s

20-Gb/s over 30m Coax Cable -29dB

Measurement Bottlenecks 75W cable driver to be measured in a 50W environment Eventual packaging will solve this problem How will S21 and S22 change when driving a 75W load when compared to the 50W measurement? S21 and S22 will improve in theory How can we verify the maximum swing to be expected in a 75W environment? Theoretically the swing driving 75W should be 1.25 times the swing driving 50W

Driver Output Impedance: Measurements vs. Simulations

DCC Control @ 40- and 30-Gb/s

SiGe BiCMOS is the best option Choice of Technology CMOS 90/65nm SiGe BiCMOS III-V Considerations SiGe BiCMOS is the best option System Integration Low cost ? High-speed (40Gb/s) T. Chalvatzis, JSSC07 40-Gb/s Retimer in 90nm CMOS – need 65nm for margin Output swing (5Vpp per side) Reliability over temperature ?

Initial Driver Design Driving a 75W coax cable with 5Vpp per side requires digital switching of ~133mA For reliable operation under large output voltage swings, high voltage HBTs (HV-HBT) are required at the output node BVCEO=3.5V fT = 75GHz fMAX = 100GHz RC time constant analysis, when the HV-HBT is biased at 0.75*JpkfT, results in a -3dB bandwidth of ~10GHz, Lumped toplogy is not an option therefore pointing to a distributed architecture (at least for the output stage) IT = 5Vpp / 37.5W = 133mA Line driver Vdd 75W

Lumped Predriver Architecture DCC current ~3.3V 1.1 - 1.8V 60W 600W Small Input Device to minimize capacitance and improve input matching without EFs ~3.3V 10mA Vdd 75W 300mV Output Swing per side: 3mA 50W INP INN 400mV 800mV 1V 1.2V DCC 5mA 10mA 20mA 40mA Amplitude Control Offset Control Input DC 1.1V - 1.8V BiCMOS cascode used in the final two stages for stability Topology is ideal for impelmenting amplitude control

40mA Output Stage 75W 75W 2mm x 66 L=0.18mm ~5V ~3.3V 8 x 5.46mm Digital 8 x 5.46mm HV-HBT 2mm x 66 L=0.18mm ~5V ~3.3V 75W 75W

T-Line Compensation T-line section Distributed T-line inductors designed to absorb the load capacitance from the DA stage minimize the impact on Z0, S21, and phase distortion