CSE 370 – Winter 2002 – Comb. Logic building blocks - 1 Overview Last lecture Design examples Today More design examples Adders (arithmetic circuits) 11/30/2018 CSE 370 – Winter 2002 – Comb. Logic building blocks - 1

CSE 370 – Winter 2002 – Comb. Logic building blocks - 2 Logical function unit Multi-purpose function block 3 control inputs to specify operation to perform on operands 2 data inputs for operands 1 output of the same bit-width as operands C0 C1 C2 Function Comments 0 0 0 1 always 1 0 0 1 A + B logical OR 0 1 0 (A • B)' logical NAND 0 1 1 A xor B logical xor 1 0 0 A xnor B logical xnor 1 0 1 A • B logical AND 1 1 0 (A + B)' logical NOR 1 1 1 0 always 0 3 control inputs: C0, C1, C2 2 data inputs: A, B 1 output: F 11/30/2018 CSE 370 – Winter 2002 – Comb. Logic building blocks - 2

CSE 370 – Winter 2002 – Comb. Logic building blocks - 3 Formalize the problem C0 C1 C2 A B F 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 0 choose implementation technology 5-variable K-map to discrete gates multiplexer implementation C2 C0 C1 0 1 2 3 4 5 6 7 S2 8:1 MUX S1 S0 F 1 0 A B A B A B 11/30/2018 CSE 370 – Winter 2002 – Comb. Logic building blocks - 3

CSE 370 – Winter 2002 – Comb. Logic building blocks - 4 ROM vs. PLA ROM approach advantageous when design time is short (no need to minimize output functions) most input combinations are needed (e.g., code converters) little sharing of product terms among output functions ROM problems size doubles for each additional input can't exploit don't cares PLA approach advantageous when design tools are available for multi-output minimization there are relatively few unique minterm combinations many minterms are shared among the output functions PAL problems constrained fan-ins on OR plane 11/30/2018 CSE 370 – Winter 2002 – Comb. Logic building blocks - 4

Regular logic structures for two-level logic ROM – full AND plane, general OR plane cheap (high-volume component) can implement any function of n inputs medium speed PAL – programmable AND plane, fixed OR plane intermediate cost can implement functions limited by number of terms high speed (only one programmable plane that is much smaller than ROM's decoder) PLA – programmable AND and OR planes most expensive (most complex in design, need more sophisticated tools) can implement any function up to a product term limit slow (two programmable planes) 11/30/2018 CSE 370 – Winter 2002 – Comb. Logic building blocks - 5

Regular logic structures for multi-level logic Difficult to devise a regular structure for arbitrary connections between a large set of different types of gates efficiency/speed concerns for such a structure in 467 you'll learn about field programmable gate arrays (FPGAs) that are just such programmable multi-level structures programmable multiplexers for wiring lookup tables for logic functions (programming fills in the table) multi-purpose cells (utilization is the big issue) Use multiple levels of PALs/PLAs/ROMs output intermediate result make it an input to be used in further logic 11/30/2018 CSE 370 – Winter 2002 – Comb. Logic building blocks - 6

Combinational logic implementation summary Multi-level logic conversion to NAND-NAND and NOR-NOR networks transition from simple gates to more complex gate building blocks reduced gate count, fan-ins, potentially faster more levels, harder to design Time response in combinational networks gate delays and timing waveforms hazards/glitches (what they are and why they happen) Regular logic multiplexers/decoders ROMs PLAs/PALs advantages/disadvantages of each 11/30/2018 CSE 370 – Winter 2002 – Comb. Logic building blocks - 7

CSE 370 – Winter 2002 – Comb. Logic building blocks - 8 Arithmetic circuits Excellent examples of combinational logic design Time vs. space trade-offs doing things fast may require more logic and thus more space example: carry lookahead logic Arithmetic and logic units general-purpose building blocks critical components of processor datapaths used within most computer instructions 11/30/2018 CSE 370 – Winter 2002 – Comb. Logic building blocks - 8

2s complement (fast review) If N is a positive number, then the negative of N ( its 2s complement or N* ) is N* = 2n – N, where n is the number of bits in the representation example: 2s complement of 7 example: 2s complement of –7 shortcut: 2s complement = bit-wise complement + 1 0111 -> 1000 + 1 -> 1001 (representation of -7) 1001 -> 0110 + 1 -> 0111 (representation of 7) 4 2 = 10000 7 = 0111 1001 = repr. of –7 subtract 4 2 = 10000 –7 = 1001 0111 = repr. of 7 subtract 11/30/2018 CSE 370 – Winter 2002 – Comb. Logic building blocks - 9

2s complement addition and subtraction Simple addition and subtraction 4 + 3 7 0100 0011 0111 – 4 + (– 3) – 7 1100 1101 11001 4 – 3 1 0100 1101 10001 – 4 + 3 – 1 1100 0011 1111 11/30/2018 CSE 370 – Winter 2002 – Comb. Logic building blocks - 10

Why can the carry-out be ignored? Can't ignore it completely needed to check for overflow (see next two slides) When there is no overflow, carry-out may be true but can be ignored – M + N when N > M: M* + N = (2n – M) + N = 2n + (N – M) ignoring carry-out is just like subtracting 2n – M + – N where N + M  2n–1 (– M) + (– N) = M* + N* = (2n– M) + (2n– N) = 2n – (M + N) + 2n ignoring the carry, it is just the 2s complement representation for – (M + N) 11/30/2018 CSE 370 – Winter 2002 – Comb. Logic building blocks - 11

Overflow in 2s complement addition/subtraction Overflow conditions add two positive numbers to get a negative number add two negative numbers to get a positive number +0 +1 +2 +3 +4 +5 +6 +7 –8 –7 –6 –5 –4 –3 –2 –1 0000 0111 0011 1011 1111 1110 1101 1100 1010 1001 1000 0110 0101 0100 0010 0001 +0 +1 +2 +3 +4 +5 +6 +7 –8 –7 –6 –5 –4 –3 –2 –1 0000 0111 0011 1011 1111 1110 1101 1100 1010 1001 1000 0110 0101 0100 0010 0001 5 + 3 = –8 –7 – 2 = +7 11/30/2018 CSE 370 – Winter 2002 – Comb. Logic building blocks - 12

CSE 370 – Winter 2002 – Comb. Logic building blocks - 13 Overflow conditions Overflow when carry into sign bit position is not equal to carry-out 0 1 1 1 0 1 0 1 0 0 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1 1 1 0 1 0 1 1 1 5 3 – 8 – 7 – 2 7 overflow overflow 0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 0 0 0 5 2 7 – 3 – 5 – 8 no overflow no overflow 11/30/2018 CSE 370 – Winter 2002 – Comb. Logic building blocks - 13