Patent Portfolio on Chip Design for Smart Memories

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Presentation transcript:

Patent Portfolio on Chip Design for Smart Memories

Ginkgo Patent Portfolio: topics & targets Put simply, this portfolio is related to: 1 Design on memory, focusing on low power consumption as well as offering area saving integrated circuit design solutions 2 FDSOI design for core circuits Targets: 1 Target devices: DRAM, eDRAM, FPGA, Flash, FBC, SRAM,… 2 Target markets: stand-alone memory, embedded memory, consumer logic 30/11/2018

Patent Portfolio Proposed Portfolio comprising 34 patent families corresponding to 188 current patent applications filed between 2009 - 2014, with majority of filings in 2010-2011 157 granted (83.5 %)  strong advantage! 31 pending (16.5 %) Geographical coverage USA France South Korea China Germany Taiwan Great Britain Singapore Japan 30/11/2018

Patent Portfolio Assessment Key and Support patents in nearly every ‘Product Class’ considered Broad distribution between Technology and Design/Architecture Strong Design patent portfolio 30/11/2018

Patent Portfolio Assessment DRAM Flash FBC SRAM E. Memories FPGA Misc. Key Patents 12 13 10 8 Support Patents 5 4 3 2 Total 17 16 14 11 Product Class Patent Type DRAM: Dynamic Random Access Memory FBC: Floating Body Cells SRAM: Static Random Access Memory E. Memories: Emerging Memories FPGA: Field Programmable Gate Arrays Key patents: patents specific and important for Product Class Support patents: unspecific patents but usable for Product Class 30/11/2018

Patent Portfolio Assessment DRAM Material/Process Device Design Architecture Key Patents 3 1 5 2 Support Patents Total 6 4 Process/Material: All patents related to processing, materials, wafers, etc. Device: All patents for devices like transistors, metallization Design: All patents for arrangements of devices like SRAMS, Inverters, etc Architecture: All patents for arrangements of design elements 30/11/2018

Patent Portfolio Assessment Flash Material/Process Device Design Architecture Key Patents 3 6 Support Patents 2 1 Total 5 4 FBC Material/Process Device Design Architecture Key Patents 3 1 4 2 Support Patents Total 5 SRAM Key Patents 3 6 Support Patents 2 1 Total 5 4 Emerging Memories Key Patents 2 1 5 3 Support Patents Total FPGA Key Patents 3 6 Support Patents 2 1 Total 5 4 Miscellaneous Key Patents 1 3 2 Support Patents Total 4 6 5 30/11/2018

Patent Portfolio Assessment Patent list link : SOITEC IP porfolio.docx 30/11/2018

Main Value Proposition 1 Lower Cost of Ownership: DRAM CoO reduction > 40% through FDSOI optimized circuit solutions 2 Efficient Design Architecture: denser block organization smaller circuit blocks integration of new circuits for yield enhancement 3 Lower Power Consumption: Reduction of static and dynamic power consumption >50% 30/11/2018 C3 / SECRET TITLE

Memory benefits on peripheral circuits 1 Area reduction: Less sensitivity to variability (FD)) Innovative and denser design techniques 2 Performance increase: Higher efficiency Circuit simplification (less stages to propagate through, less noise generation) Lower Impedance 3 Power reduction: Power reduced by back gate control and smaller transistor count this is a very powerful tool! Size reduction of periphery circuits and in particular of the refresh circuits smaller devices New approach aiming structural, material as well as substrate change 30/11/2018