Chapter 1 and 2 review CMOS Devices and models Fabrication process

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Presentation transcript:

Chapter 1 and 2 review CMOS Devices and models Fabrication process Diodes Transistors Resistors Capacitors Fabrication process Layout

Capacitors conductor-insulator-conductor C = C0A or C0L Poly-poly cap Fringe cap Chapter 1 Figure 37

MOS cap: for NMOS, connect D, S, B and gnd together, G free; for PMOS, connect D, S, and well together, both terminals free. Chapter 1 Figure 36 There are many more capacitors (any time you have conductor-insulator-conductor). Most are parasitic. Most are nonlinear.

Resistors R = R*(# of squares)  Rs*(L/W) Chapter 1 Figure 34 Types of sheet materials: poly1, poly2, metals, well, diffusion, substrate transistors (channel inversion layer)

Example: well resistor Chapter 1 Figure 35

MOSIS ON 0.5 um process

Diodes Chapter 1 Figure 01 ID = Isexp(VD/VT), VT = kT/q

Cj junction capacitance tT depends on materials gd = ID/VT, rd = 1/gd Cd = tT*ID/VT Cj junction capacitance tT depends on materials Chapter 1 Figure 04 Cd, Cj, gd all depend on bias voltage VD For reverse bias, gd = 0

NMOS transistor Chapter 1 Figure 10 G S D B

Square law model: DC large signal triode saturation Chapter 1 Figure 14 = VGS – Vtn deep triode

Small signal model: low freq Chapter 1 Figure 17

NMOS with parasitic caps Chapter 1 Figure 21

Frequency dependent model Chapter 1 Figure 22

Key MOS parameters Intrinsic gain: A0 = gmrds = gm/gds Chapter 1 Figure 26

Key MOS parameters Transit frequency: frequency at which current gain reduces to unity Chapter 1 Figure 27 vgss(Cgs+Cgd)= When iin=iout: s = gm/(Cgs+Cgd)  gm/Cgs

Mobility limited, linear in Vgs Chapter 1 Figure 30 Subthreshold Weak inversion

Chapter 1 Figure 28

Chapter 1 Table 01

Chapter 1 Table 04