SOC Design Lecture 4 Bus and AMBA Introduction

Road without Traffic Lights

Communication between Multiples

Bus bus

Two Types of Connections Register Register Register Register 화면 내 공간적 유사성을 보여주는 그림 삽입 필요 Register Register Register Register Register Register Point-to-Point Connection Common Bus-based Connection

AMBA Stands for Advanced Microcontroller Bus Architecture Developed by ARM in 1990s (England) ARM also developed ARM RISC which is now the mostly widely used RISC core and that makes AMBA most popular BUS in SOC world.

Typical AMBA System ASB is not used these days.

Key AMBA Version AMBA 2.0 : AHB, APB, ASB AMBA 3.0 : AXI

Master and Slave Concept 화면 내 공간적 유사성을 보여주는 그림 삽입 필요 A can initiate a data transfer. (Write operation in this case.) B only responses to a A’s request. A is called a master and B is called a slave.

How about read operation? Which one is a master?

Bus Again In such simple case we do not need a bus.

AMBA for Multiple Masters & Slaves AMBA consists of Master, Slave, Arbiter, Mux, and Decoder. HADDR is the address from master to slave. HWDATA is the data from master to slave. HRDATA is the data from slave to master.

Number of Cases about BUS Single Master, Single Slave Multi Master, Single Slave Single Master, Multi Slave Multi Master, Multi Slave 화면 내 공간적 유사성을 보여주는 그림 삽입 필요

Multi Master, Single Slave (MMSS) 화면 내 공간적 유사성을 보여주는 그림 삽입 필요 There’s a Mux. How do we make a “Master Selection” signal?

Arbiter 화면 내 공간적 유사성을 보여주는 그림 삽입 필요 When a master wants to transfer data, it sends a request signal to arbiter. If arbiter grants the request, then the master transfers data.

Single Master, Multi Slave (SMMS) 화면 내 공간적 유사성을 보여주는 그림 삽입 필요 There’s a Mux, but situation is different from MMSS case. How do we make a slave selection signal?

Decoder 화면 내 공간적 유사성을 보여주는 그림 삽입 필요 Slave A & B must have a different address. ex) Slave A : 0x0 ~ 0x3FFF, Slave B : 0x4000 ~ 0x7FFF Decoder decodes an address from master, and make a selection signal.

AMBA for Multiple Masters & Multiple Slaves

AMBA Signals Signal Description HRESET Reset HADDR Address HWDATA Data from master to slave HWRITE Write Enable HRDATA Data from slave to master HREADY Indicates slave is ready HREQUES Tx Request from Master number x to Arbiter HGRANTx Grant from Arbiter to Master number x HSELx Section Signal from Decoder to Slave …

What about human laws? There are millions of laws. Do you have to do all the legal actions everyday? No. You just need to do what you want. Just do not violate the laws. So, if you need a simple job, you can use a few AMBA signals only. Let’s find the “minimal set” of AMBA signal for our goal.

Single Master Single Slave (SM SS)

SM SS Write and Read HCLK HADDR HWRITE HWDATA

AXI

Channels for AXI Read Address Channel (AR….) Read Data Channel (R…..) Write Address Channel (AW….) Write Data Channel (W…..) Write Response Channel (B….)

AHB vs. AXI AHB AXI

AXI Read Concept

Read Address Channel Signal

Read Data Channel Signal

Read Address and Data

Write Address Channel Signal

Write Data Channel Signal

Write Address and Data

Write Response Channel Signal

Write Address, Data and Response

NOC (Network On a Chip)