Computer Architecture Exception Handling and Advanced Pipelining

Datapath with Controls to Handle Exceptions

Exception Handling Example overflow exception

Exception Handling Example start of exception handling routine

Advanced Pipelining Superpipelining Superscalar Dynamic Pipeline Scheduling

Superpipelining IF-1 ID EX-1 EX-2 MEM WB IF-1 ID EX-1 EX-2 MEM WB IF-1

Superscalar IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX ALU or Branch Load or Store IF ID EX MEM WB ALU or Branch Load or Store IF ID EX MEM WB ALU or Branch Load or Store IF ID EX MEM WB ALU or Branch Load or Store IF ID EX MEM WB

Superscalar Pipeline

Simple Superscalar Code Scheduling Loop: lw $t0, 0($s1) # $t0=array element addu $t0, $t0, $s2 # add scalar in $s2 sw $t0, 0($s1) # store result addi $s1, $s1, -4 # decrement pointer bne $s1, $zero, Loop # branch $s1!=0

Scheduled Code

Loop Unrolling

Dynamic Pipeline Scheduling Example: Power PC 604, Pentium Pro, Alpha 21264, MIPS R10000

Dynamic Pipeline Scheduling Overcome key performance limitations of in-order pipeline instruction execution Structural hazard Replicate pipelines Data hazard Execute instructions out of program order Rename registers as needed Control hazard Execute instructions speculatively across branches

Dynamic Branch Prediction One-bit prediction scheme not-taken taken not-taken predict not-taken predict taken taken Problem : Loop case

Dynamic Branch Prediction Two-bit prediction scheme taken not-taken predict taken predict taken taken not-taken taken not-taken predict not-taken predict not-taken taken not-taken

Summary Three major handles in pipelined implementation Structural hazard Data hazard Control hazard Advanced pipelining Superpipelining (clock cycle time ↓) Superscalar (CPI ↓, possibly < 1) Dynamic pipeline scheduling Structural hazard: resource replication Data Hazard: out-of-order execution Register renaming Control Hazard: speculative execution