Systems Architecture II September 4, 1997 Systems Architecture II (CS 282-001) Lecture 4: Pipelined Datapath and Control* Jeremy R. Johnson Wed. June 27, 2001 *This lecture was derived from material in the text (Chap. 6). All figures from Computer Organization and Design: The Hardware/Software Approach, Second Edition, by David Patterson and John Hennessy, are copyrighted material (COPYRIGHT 1998 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED). June 27, 2001 Systems Architecture II

Systems Architecture II September 4, 1997 Introduction Objective: To understand the modifications to the datapath and control used in the single cycle implementation of MIPS needed to support pipelining. Key idea: Separate datapath into 5 pieces, one for each stage of the pipeline. Add registers between pieces to hold the information specific to the currently executing instruction. Note: We will ignore the difficulties due to hazards in this lecture Topics Review of the single cycle implementation of MIPS Pipelined datapath Graphical representation of pipelines (multiple and single clock-cycle pipelining diagrams) Adding control to the pipelined datapath June 27, 2001 Systems Architecture II

Pipeline Stages for MIPS Instruction Execution There are five stages: IF: Fetch instruction ID: Instruction decode and register file EX: Execution or address calculation MEM: Data memory access WB: Write back June 27, 2001 Systems Architecture II

Single-cycle Datapath June 27, 2001 Systems Architecture II

Instruction Execution June 27, 2001 Systems Architecture II

Systems Architecture II Pipeline Registers June 27, 2001 Systems Architecture II

Load Instruction (stages 1-3) June 27, 2001 Systems Architecture II

Load Instruction (stages 4-5) June 27, 2001 Systems Architecture II

Store Instruction (stages 3-5) June 27, 2001 Systems Architecture II

Correction to Datapath for Load June 27, 2001 Systems Architecture II

Datapath with Control Signals June 27, 2001 Systems Architecture II

Systems Architecture II ALU Control June 27, 2001 Systems Architecture II

Systems Architecture II Control Signals RegDst - register destination number if deasserted then rt field (bits 20-16) if asserted then rd field (bits 15-11) RegWrite - write to register file when asserted ALUSrc - select second input to ALU if deasserted then second register file output if asserted then sign-extended 16 bits of instruction PCSrc - select input to PC if deasserted then PC+4 if asserted then branch target MemRead - read from memory if asserted MemWrite - write to memory if asserted MemtoReg - select register write data source if deasserted then ALU output if asserted then data memory June 27, 2001 Systems Architecture II

Passing Control through the Pipeline June 27, 2001 Systems Architecture II

Datapath with Control Signals June 27, 2001 Systems Architecture II

Systems Architecture II Example lw $10, 20($1) sub $11, $2, $3 and $12, $4, $5 or $13, $6, $7 add $14, $8, $9 June 27, 2001 Systems Architecture II

Systems Architecture II June 27, 2001 Systems Architecture II

Systems Architecture II June 27, 2001 Systems Architecture II

Systems Architecture II June 27, 2001 Systems Architecture II

Systems Architecture II June 27, 2001 Systems Architecture II

Systems Architecture II June 27, 2001 Systems Architecture II

Systems Architecture II June 27, 2001 Systems Architecture II

Systems Architecture II June 27, 2001 Systems Architecture II

Systems Architecture II June 27, 2001 Systems Architecture II

Systems Architecture II June 27, 2001 Systems Architecture II