Advanced Digital Design Asynchronous Design: DI Methods by A. Steininger and M. Delvai Vienna University of Technology

© A. Steininger & M. Delvai / TU Vienna Outline Delay Insensitive design - principle NULL-Convention Logic Code conditions for DI logic Delay models Four-State Logic Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Asynchronous Philosophy recall Asynchronous Philosophy „The control flow requires agreement between source and sink. For this purpose they need to communicate“ Source indicates capture condition for sink. Sink indicates issue condition for source. „HANDSHAKE“ Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna recall Handshake Principle REQ: „Data word valid, you can use it“ When can SNK use its input? When it is valid and consistent f(x) SRC SNK When can SRC apply the next input? When SNK has consumed the previous one ACK: „Data word consumed, send the next“ Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

A very Important Detail recall A very Important Detail The handshake establishes a closed-loop control for the data flow between sender and receiver This makes operation more robust than in the synchronous (= open-loop) case The art of asynchronous design is to make many of these closed loops interoperate properly This is much more complicated than a synchronous design. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Bundled Data at a Glance single-rail data coding 4- or 2-phase handshake Source: [Sparso 06] Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Very disappointing… For a closed loop we need to measure the quantity of interest So far we have not done that: We have not measured validity & consistency We have used time as an indirect measure instead Thus Bounded Delay methods do not provide the benefits of a closed loop BUT: Can we measure validity & consistency at all? Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna recall Criticality of ACK f(x) FF2 SRC SNK „latch!“ cannot measure „act of latching“ as an event use latching command instead fork produces race between trigger process and next data wave race is uncritical (but still exists!) Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna recall Criticality of REQ f(x) SRC SNK cannot use issue trigger as an event: produces unacceptable race between data and REQ must introduce timer (bounded delay) OR: find better event (downstream) completion detection Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Completion Detection In order to judge when data are valid & consistent we need to be able to see when this is NOT the case not possible with Boolean logic need representation for INVALID an ACK in parallel to data (bundled data) will always cause a race need more than two signal states for every individual bit (!) need more than one rail per bit Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Multi-level Logic use more than two (e.g. three) voltage levels per rail allows to express „invalid“ in the currently „forbidden“ area between HI and „LO“ requires two thresholds for every gate input output must be able to drive three different levels reliably causes substantial technological problems not further pursued Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna recall Our Options We must only use consistent input vectors How can we tell an input vector is consistent? (1) use TIME to mark consistent phases synchronous approach / global time base asynchronous/bounded delay (2) use CODING to add information asynchronous/delay insensitive Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna recall Terminology consistent DW: all bits belong to the same context valid signal: result of function applied to consistent DW Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna NULL Convention Logic Add the value NULL to the alphabet Signal X X.a X.b meaning NULL (N) 1 TRUE (T) FALSE (F) illegal two-rail coding: X.a X X.b „DATA“ Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna NCL Functions AND T F N OR T F N NOT T F N naive approach: if any input is „N“ then output „N“ Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna NCL Flow Control NULL waves enframe DATA waves Completion detection = check wether all bits are „DATA“ (completeness of DATA) NULL TRUE NULL TRUE NULL TRUE NULL FALSE NULL FALSE NULL TRUE NULL TRUE NULL FALSE t consistent DATA Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Still Problems … What about this situation? Fast bits may catch up with a slow bit from the previous word. The word containing the „old“ bit is considered consistent! output NULL DATA NULL DATA NULL TRUE NULL TRUE NULL TRUE NULL FALSE NULL TRUE NULL TRUE NULL FALSE t consistent DATA Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Solution Principle Enforce „completeness of NULL“ as well: The output must not go to NULL before all inputs have changed to NULL In a closed loop configuration this keeps the slow paths in synchrony with the fast ones We need different truth table when output is NULL Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Two Truth Tables for DATA waves for NULL waves AND T F N AND T F N D D … DATA (T or F) must hold output in last valid state before new input is complete need „hysteresis“ need to consider current output in truth table Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Feedback Gate N T A N F N F & B F N Y‘ Y Y N F T A B Y‘ unstable (Y  Y‘) Lecture "Advanced Digital Design" A © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna No more Problems … Have we solved the problem? YES! The output now remains at DATA with the slowest bit, thus inhibiting (via the closed loop) the fast bits to convey the next DATA wave. output NULL DATA NULL TRUE NULL NULL TRUE NULL FALSE NULL NULL TRUE NULL t consistent DATA Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna NCL Gates The desired hysteresis requires an NCL gate to hold its output until all inputs are DATA or all inputs are NULL need storage capability (or feedback loop) even in combi- national gate X1.a X1 X1.b Mem Y.a Y Y.b X2.a X2 Mem X2.b Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

NCL Gate Implementation p- and n-stack not dual figure shown for one output rail only X1.a X1 X1.b Mem Y.a Y Y.b X2.a memory cell at output X2 Mem X2.b CMOS-Transistors only but no standard cells [G. Sobelmann, K. Fant: CMOS Circuit Design of Threshold Gates with Hysteresis] Lecture "Advanced Digital Design" A © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna The Charme of NCL self-regulating data flow in a NULL initialized circuit a DATA front will propagate towards the output alternating waves of NULL and DATA pace the data flow (which, in some sense, forms the „clock“) based on direct assessment of validity & consistency no delay assumptions necessary (ideally), no „worst case“, … globally applicable solution Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Validity and Consistency Consistency (multiple bits @ input) all bits that are combined are valid and belong to the same context Validity (single bit @ output) the bit is the stable result of a combination of consistent bits Consistency implies validity (per definition) but NOT vice versa! Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Val. & Consistcy. in NCL Validity: Consistency: output is changed only when consistent input is available („hold“ in truth table) coding ensures direct transistion from valid code to another (NULL is valid but spacer only) continuous validity Consistency: NULL spacer between DATA waves allows identification of context synchronization of context by virtue of „completeness of NULL“ condition no timing assumptions! CODING indicates consistency Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna What about sync. & BD? Timing ensures that every data item is both valid and consistent at the time it is used: choice of clock period (sync) choice of delay values (BD) In contrast to NCL (temporary) invalidity of data is admitted. No explicit measures (other than timing) are taken/necessary to cope with these issues. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Softening the restrictions recall Softening the restrictions synchronous model known bounds for delays, global timing bounded delay model (fundamental) known bounds for absolute delays, local timing scalable-delay-insensitive model bounds for relative deviation between delays known quasi-delay-insensitive output paths of a fork have same delay delay insensitive no restrictions on delays (just finite) syn: optimistisch, immer schwieriger zu erfüllen Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Some Terminology Source: [Sparso 06] speed-independent: dA, dB, dC arbitrary; d1=d2=d3=0 delay-insensitive: dA, dB, dC, d1, d2, d3 arbitrary quasi-delay-insensitive: dA, dB, dC, d1, d2 arbitrary; d3=d2 self-timed: other general word for „asynchronous“ Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna NCL: A Brief Summary validity & consistency directly visible no timing assumptions required (ideally) „delay insensitive“ (ideally) suitable for CMOS implementation coding of one bit on two rails 2 memory cells per combinational output efficiency: 50% of the data flow are unproductive NULL waves patented und industrially used Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna NCL at a Glance dual-rail data coding 4-phase handshake Source: [Sparso 06] Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna recall Our Options We must only use consistent input vectors How can we tell an input vector is consistent? (1) use TIME to mark consistent phases synchronous approach / global time base asynchronous/bounded delay (2) use CODING to add information asynchronous/delay insensitive ARE THERE OTHER CODING OPTIONS? Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Conditions for DI Coding (C1) Identification of every context switch It must be possible to clearly separate two successive data words under all circumstances (C2) Unique context membership The transition from one valid code word to the next must be unambiguous, i.e. no intermediate state may be a valid code Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Conditions for DI coding (C1) Identification of every context switch It must be possible to clearly separate two successive data words under all circumstances 0,0,0 0,0,0 ? Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Conditions for DI coding (C1) Identification of every context switch It must be possible to clearly separate two successive data words under all circumstances (C2) Unique context membership The transition from one valid code word to the next must be unambiguous, i.e. no intermediate state may be a valid code Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Conditions for DI coding 0,0,0 1,0,0 1,0,1 1,1,1 (C2) Unique context membership The transition from one valid code word to the next must be unambiguous, i.e. no intermediate state may be a valid code ? Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

What about NCL‘s Coding (C1) Return to NULL forces separation between successive data waves (C2) Coding scheme guarantees direct switch from one legal value to next (only one rail changes!) Signal X X.a X.b value NULL 1 TRUE FALSE illegal Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Synchronization of Waves NULL 0,1 NULL 1,0 NULL A B Y 1 A & Y B no glitch! N N N successive „0“s clearly separable Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna NCL vs. Trans. Signaling Transition Signaling NULL-Convention Logic A=0 A=1 A=1 A=1 A=0 A0 A1 A=0 A=1 A=1 A=1 A=0 A0 A1 Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna More Efficient Coding? NCL employs a 4-phase (RTZ) version of transition signaling. The „return to zero“ is due to the NULL waves. The NULL waves are unproductive and hence undesired. Can we employ 2-phase (NRZ) transition signaling instead? Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Four-State Logic (FSL) Use 2 codes per logic value two-rail coding: X.a X X.b Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna FSL Flow Control Alternate code sets („phase“) Completion detection: Check whether all bits belong to the same phase NCL FSL NULL H h TRUE NULL L TRUE l NULL L l TRUE NULL L FALSE l H NULL l FALSE H NULL h TRUE H NULL TRUE h NULL H h FALSE t consistent phase j1 konsistent phase j0 Lecture "Advanced Digital Design" A © A. Steininger & M. Delvai / TU Vienna

FSL AND-Gate: Truth Table IN_2 Y l h L H * IN_1 * … hold last valid output Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Four-State Logic (FSL) An FSL gate holds its output until all inputs are in the same phase need storage capability (or feedback loop) even in combi- national gate X1.a X1 X1.b Mem Y.a Y Y.b X2.a X2 Mem X2.b Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

FSL and Code Conditions (C1) Phase change forces separation between successive data waves (C2) Coding scheme guarantees direct switch from one legal value in one phase to legal value in next phase (only one rail changes!) Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Synchronization of Waves 0,1 1,0 A B Y 1 A & Y B successive „0“s clearly separable no glitch! F0 F1 Lecture "Advanced Digital Design" A © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna FSL: A Brief Summary FSL retains all the charme of NCL FSL provides double data throughput implementation of 2-phase scheme tends to require more efforts (remains to be investigated) Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna FSL at a Glance dual-rail data coding 2-phase handshake X1.a a b j0 LO HI 1 j1 X1.b … Xn.a Xn.b Ack X1 valid valid valid … Xn valid valid valid Ack Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Gain of Delay Insensitive  need to determine clock period circuit functionality is technology dependent considerable design efforts, large design loops need to make worst-case assumptions necessarily pessimistic no robustness wrt. exceeding them need to maintain global synchrony clock distribution problems power consumption problems   Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Comparing the Styles handshake style 4-phase (RTZ) 2-phase (NRZ) data coding single rail bundled data multirail NCL FSL, LEDR level signaling transition signaling single rail multirail delay model bounded QDI ACK explicit handshake REQ explicit compl. det. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Power saving by multirail one-of-n-coding in combination with 4-phase (RTZ) fulfills coding requirements two transitions per ld(n) bit wider bus => fewer transitions trade area for power saving n-of-n and 1-of-n are the extremes; the whole solution space is k-of-n code 0000 0001 0010 0100 1000 data(j,k) NULL 00 01 10 11 Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna The top 10 for async. achieve average case performance consume power only when needed easy modular composition no clock alignment at interfaces metastability has time to resolve avoid clock distribution problems exploit concurrence more gracefully intellectual challenge intrinsic elegance global synchrony does not exist anyway [Al Davis, Async’94] Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna The truth … is, that just „going asynchronous“ is not beneficial, but in certain cases with carefully chosen method and implementation… simple syn=> asyn conversion does NOT do the job! a mix of different protocols & timing models is required tuning of library cells … asynchronous design can have crucial advantages, in real industrial problems Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna